Description : The digital logic family which has the lowest propagation delay time is (A) ECL (B) TTL (C) CMOS (D) PMOS
Last Answer : Ans: A The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).
Description : The digital logic family which has minimum power dissipation is (A) TTL (B) RTL (C) DTL (D) CMOS
Last Answer : (D) CMOS The digital logic family which has minimum power dissipation is CMOS. (CMOS being an unipolar logic family, occupy a very small fraction of silicon Chip area)
Description : How many select lines will a 32:1 multiplexer will have (A) 5. (B) 8. (C) 9. (D) 11.
Last Answer : (A) 5.
Description : The number of control lines for a 8 – to – 1 multiplexer is (A) 2 (B) 3 (C) 4 (D) 5
Last Answer : Ans: B The number of control lines for an 8 to 1 Multiplexer is 3 (The control signals are used to steer any one of the 8 inputs to the output)
Description : Which of following consume minimum power (A) TTL. (B) CMOS. (C) DTL. (D) RTL.
Last Answer : Ans: B CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS transistors are connected in complimentary mode, such that one device is ON & one is OFF.
Description : Which of the following is the fastest logic? (A) ECL (B) TTL (C) CMOS (D) LSI
Last Answer : (A) ECL
Description : The MSI chip 7474 is (A) Dual edge triggered JK flip-flop (TTL). (B) Dual edge triggered D flip-flop (CMOS). (C) Dual edge triggered D flip-flop (TTL). (D) Dual edge triggered JK flip-flop (CMOS).
Last Answer : Ans: C MSI chip 7474 dual edge triggered D Flip-Flop.
Description : CMOS circuits consume power (A) Equal to TTL (B) Less than TTL (C) Twice of TTL (D) Thrice of TTL
Last Answer : Ans: B As in CMOS one device is ON & one is Always OFF so power consumption is low.
Description : Which TTL logic gate is used for wired ANDing (A) Open collector output (B) Totem Pole (C) Tri state output (D) ECL gates
Last Answer : Ans: A Open collector output.
Description : Which of the following is the fastest logic (A) TTL (B) ECL (C) CMOS (D) LSI
Last Answer : Ans: B ECL is the fastest logic family of all logic families. (High speeds are possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated.
Description : Define multiplexer
Last Answer : Multiplexer is a digital switch. If allows digital information from several sources to be routed onto a single output line.
Description : The number of control lines for 32 to 1 multiplexer is (A) 4. (B) 5. (C) 16. (D) 6.
Last Answer : Ans: B The number of control lines for 32 (2^5) and to select one input among them total 5 select lines are required.
Description : The number of control lines for 16 to 1 multiplexer is (A) 2. (B) 4. (C) 3. (D) 5.
Last Answer : (B) 4.
Description : How many select lines will a 16 to 1 multiplexer will have (A) 4 (B) 3 (C) 5 (D) 1
Last Answer : (A) 4
Description : A device which converts BCD to Seven Segment is called (A) Encoder (B) Decoder (C) Multiplexer (D) Demultiplexer
Last Answer : Ans: B A device which converts BCD to Seven Segment is called DECODER. (A decoder coverts binary words into alphanumeric characters.)
Description : The device which changes from serial data to parallel data is (A) COUNTER (B) MULTIPLEXER (C) DEMULTIPLEXER (D) FLIP-FLOP
Last Answer : Ans: C The device which changes from serial data to parallel data is demultiplexer. (A demultiplexer takes in data from one line and directs it to any of its N outputs depending on the status of the select inputs.)
Description : How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB (A) 1, 1 (B) 4, 2 (C) 3, 2 (D) 2, 3
Last Answer : Ans: A There are three product terms, so three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.
Description : The output of a JK flipflop with asynchronous preset and clear inputs is 1'. The output can be changed to 0' with one of the following conditions. (A) By applying J = 0, K = 0 and using a clock. (B) ... (C) By applying J = 1, K = 1 and using the clock. (D) By applying a synchronous preset input.
Last Answer : Ans: C Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of the present state.
Description : An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately (A) 1 MHz. (B) 500 MHz. (C) 2 MHz. (D) 4 MHz.
Last Answer : Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.
Description : When an input signal A=11001 is applied to a NOT gate serially, its output signal is (A) 00111. (B) 00110. (C) 10101. (D) 11001.
Last Answer : When an input signal A=01001 is applied to a NOT gate serially , it's output signal is
Description : How many two-input AND and OR gates are required to realize Y=CD+EF+G (A) 2,2. (B) 2,3. (C) 3,3. (D) none of these.
Last Answer : Ans: A Y=CD+EF+G Number of two input AND gates=2 Number of two input OR gates = 2 One OR gate to OR CD and EF and next to OR of G & output of first OR gate.
Description : When the set of input data to an even parity generator is 0111, the output will be (A) 1 (B) 0 (C) Unpredictable (D) Depends on the previous input
Last Answer : Ans: B In even parity generator if number of 1 is odd then output will be zero.
Description : In successive-approximation A/D converter, offset voltage equal to 1/2 LSB is added to the D/A converter's output. This is done to (A) Improve the speed of operation. (B) Reduce the maximum ... Increase the number of bits at the output. (D) Increase the range of input voltage that can be converted
Last Answer : (B) Reduce the maximum quantization error.
Description : If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is (A) 1000 Hz (B) 500 Hz (C) 333 Hz (D) 12.5 Hz.
Last Answer : (D) 12.5 Hz.
Description : Define Asynchronous sequential circuit?
Last Answer : In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.
Description : Define synchronous sequential circuit
Last Answer : In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time.
Description : A full adder logic circuit will have (A) Two inputs and one output. (B) Three inputs and three outputs. (C) Two inputs and two outputs. (D) Three inputs and two outputs.
Last Answer : Ans: D A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.
Description : What is the decimal value of 2-3? 74) A) 0.25 B) 0.75 C) 0.125 D) 0.8
Last Answer : C) 0.125
Description : What numeric symbols are used in the binary number system? 58) A) 0 through 8 B) 0, 1, 2 C) 1, 2 D) 0, 1
Last Answer : D) 0, 1
Description : What is the decimal value of 23? 27) A) 4 B) 8 C) 2 D) 6
Last Answer : A) 00010000
Description : The decimal equivalent of binary 1010000 is ________. 8) A) 9610 B) 8010 C) 7810 D) 8410
Last Answer : A) 9610
Description : How many address bits are required to represent 4K memory (A) 5 bits. (B) 12 bits. (C) 8 bits. (D) 10 bits.
Last Answer : (B) 12 bits.
Description : How many flip-flops are required to construct mod 30 counter (A) 5 (B) 6 (C) 4 (D) 8
Last Answer : (A) 5
Description : Which of the following memories stores the most number of bits (A) a 5M×8 memory. (B) a 1M × 16 memory. (C) a 5M × 4 memory. (D) a 1M ×12 memory.
Last Answer : Ans: A 5Mx8 = 5 x 220 x 8 = 40M (max)
Description : 1’s complement representation of decimal number of -17 by using 8 bit representation is (A) 1110 1110 (B) 1101 1101 (C) 1100 1100 (D) 0001 0001
Last Answer : (A) 1110 1110
Description : Words having 8-bits are to be stored into computer memory. The number of lines required for writing into memory are (A) 1. (B) 2. (C) 4. (D) 8.
Last Answer : Ans: D Because 8-bit words required 8 bit data lines.
Description : -8 is equal to signed binary number (A) 10001000 (B) 00001000 (C) 10000000 (D) 11000000
Last Answer : (A) 10001000
Description : TTL logic family is most popularly used industries because it 1.provides greater operating speed 2.has a good fan in & fan out 3.has easy interface with other digital circuitry 4.all the above
Last Answer : It is a basically a bipolar circuit which has TTL band hate fan fan out
Description : What are the different types of shift type?
Last Answer : There are five types. They are, Serial In Serial Out Shift Register Serial In Parallel Out Shift Register Parallel In Serial Out Shift Register Parallel In Parallel Out Shift Register Bidirectional Shift Register
Description : Define shift registers.
Last Answer : The binary information in a register can be moved from stage to stage within the register or into or out of the register upon application of clock ... arithmetic and logic operations used in microprocessors. This gives rise to group of registers called shift registers.
Description : Define registers.
Last Answer : A register is a group of flip-flops flip-flop can store one bit information. So an n-bit register has a group of n flip-flops and is capable of storing any binary information/number containing n-bits.
Description : What is a master-slave flip-flop?
Last Answer : A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.
Description : What is edge-triggered flip-flop?
Last Answer : The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means that the flip-flop changes state either at the positive ... negative edge of the clock pulse and it is sensitive to its inputs only at this transition of the clock.
Description : Define race around condition.
Last Answer : In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input. Due to this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This condition iscalled ‘race around condition’.
Description : What is the operation of T flip-flop?
Last Answer : T flip-flop is also known as Toggle flip-flop. • When T=0 there is no change in the output. • When T=1 the output switch to the complement state (ie) the output toggles.
Description : What is the operation of JK flip-flop?
Last Answer : When K input is low and J input is high the Q output of flip-flop is set. When K input is high and J input is low the Q output of flip-flop is reset. When both the inputs ... are high it is possible to set or reset the flip-flop (ie) the output toggle on the next positive clock edge.
Description : What is the operation of D flip-flop?
Last Answer : In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.
Description : What are the different types of flip-flop?
Last Answer : There are various types of flip flops. Some of them are mentioned below they are, RS flip-flop SR flip-flop D flip-flop JK flip-flop T flip-flop
Description : Define Flip flop.
Last Answer : The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an input signal to change its state.