Description : Which of the following is the fastest logic? (A) ECL (B) TTL (C) CMOS (D) LSI
Last Answer : (A) ECL
Description : The digital logic family which has the lowest propagation delay time is (A) ECL (B) TTL (C) CMOS (D) PMOS
Last Answer : Ans: A The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).
Description : Which of the following is the fastest logic (A) TTL (B) ECL (C) CMOS (D) LSI
Last Answer : Ans: B ECL is the fastest logic family of all logic families. (High speeds are possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated.
Description : In standard TTL gates, the totem pole output stage is primarily used to (A) increase the noise margin of the gate (B) decrease the output switching delay (C) facilitate a wired OR logic connection (D) increase the output impedance of the circuit
Last Answer : In standard TTL gates, the totem pole output stage is primarily used to decrease the output switching delay
Description : The digital logic family which has minimum power dissipation is (A) TTL (B) RTL (C) DTL (D) CMOS
Last Answer : (D) CMOS The digital logic family which has minimum power dissipation is CMOS. (CMOS being an unipolar logic family, occupy a very small fraction of silicon Chip area)
Description : The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either (A) a NAND or an EX-OR (B) an OR or an EX-NOR (C) an AND or an EX-OR (D) a NOR or an EX-NOR
Last Answer : (D) a NOR or an EX-NOR
Description : The gates required to build a half adder are (A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate (C) EX-OR gate and AND gate (D) Four NAND gates.
Last Answer : (C) EX-OR gate and AND gate
Description : A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate? (A) OR (B) AND (C) XOR (D) NAND
Last Answer : Ans: D NAND can generate any logic function.
Description : Explain MOSFET gate drive circuit and totem pole configuration.
Last Answer : MOSFET gate drive circuit: The turning on and turning off of MOSFET can be controlled from gate to source voltage signal. If the gate to source voltage of MOSFET exceeds threshold ... this configuration, the two switches (transistors) are used in totem pole arrangement with a comparator.
Description : Which of following consume minimum power (A) TTL. (B) CMOS. (C) DTL. (D) RTL.
Last Answer : Ans: B CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS transistors are connected in complimentary mode, such that one device is ON & one is OFF.
Description : The MSI chip 7474 is (A) Dual edge triggered JK flip-flop (TTL). (B) Dual edge triggered D flip-flop (CMOS). (C) Dual edge triggered D flip-flop (TTL). (D) Dual edge triggered JK flip-flop (CMOS).
Last Answer : Ans: C MSI chip 7474 dual edge triggered D Flip-Flop.
Description : The commercially available 8-input multiplexer integrated circuit in the TTL family is (A) 7495. (B) 74153. (C) 74154. (D) 74151.
Last Answer : Ans: B MUX integrated circuit in TTL is 74153.
Description : CMOS circuits consume power (A) Equal to TTL (B) Less than TTL (C) Twice of TTL (D) Thrice of TTL
Last Answer : Ans: B As in CMOS one device is ON & one is Always OFF so power consumption is low.
Description : When an input signal A=11001 is applied to a NOT gate serially, its output signal is (A) 00111. (B) 00110. (C) 10101. (D) 11001.
Last Answer : When an input signal A=01001 is applied to a NOT gate serially , it's output signal is
Description : The NOR gate output will be low if the two inputs are (A) 00 (B) 01 (C) 10 (D) 11
Last Answer : A
Description : The NAND gate output will be low if the two inputs are (A) 00 (B) 01 (C) 10 (D) 11
Last Answer : (D) 11
Description : A full adder logic circuit will have (A) Two inputs and one output. (B) Three inputs and three outputs. (C) Two inputs and two outputs. (D) Three inputs and two outputs.
Last Answer : Ans: D A full adder circuit will add two bits and it will also accounts the carry input generated in the previous stage. Thus three inputs and two outputs (Sum and Carry) are there.
Description : Which of following are known as universal gates (A) NAND & NOR. (B) AND & OR. (C) XOR & OR. (D) None.
Last Answer : Ans: A NAND & NOR are known as universal gates, because any digital circuit can be realized completely by using either of these two gates.
Description : How many two input AND gates and two input OR gates are required to realize Y = BD+CE+AB (A) 1, 1 (B) 4, 2 (C) 3, 2 (D) 2, 3
Last Answer : Ans: A There are three product terms, so three AND gates of two inputs are required. As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.
Description : How many two-input AND and OR gates are required to realize Y=CD+EF+G (A) 2,2. (B) 2,3. (C) 3,3. (D) none of these.
Last Answer : Ans: A Y=CD+EF+G Number of two input AND gates=2 Number of two input OR gates = 2 One OR gate to OR CD and EF and next to OR of G & output of first OR gate.
Description : How many AND gates are required to realize Y = CD+EF+G (A) 4 (B) 5 (C) 3 (D) 2
Last Answer : 2
Description : DeMorgan’s first theorem shows the equivalence of (A) OR gate and Exclusive OR gate. (B) NOR gate and Bubbled AND gate. (C) NOR gate and NAND gate. (D) NAND gate and NOT gate
Last Answer : (B) NOR gate and Bubbled AND gate.
Description : In a logic circuit, the NOT gate function _____________. A. does not alter a logical input B. serves to amplify a given signal level C. must be accomplished with a common collector transistor arrangement D. reverses an input logic condition
Last Answer : Answer: D
Description : In a positive logic system, logic state 1 corresponds to (A) positive voltage (B) higher voltage level (C) zero voltage level (D) lower voltage level
Last Answer : (B) higher voltage level We decide two voltages levels for positive digital logic. Higher voltage represents logic 1 & a lower voltage represents logic 0.
Description : Which of the listed logic gates is considered to be a BASIC building block (basic logic gate) used in logic diagrams? A. NAND B. OR C. NOR D. All of the above.
Last Answer : Answer: B
Description : ECL is the fastest of all logic families. High Speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into ............... (1) Race condition (2) Saturation (3) Delay (4) High impedance
Last Answer : Answer: 2 Explanation: Emitter-coupled logic (ECL) is the fastest of all logic families and therefore is used in applications where very high speed is essential. High speeds have become ... configuration, in which they are never driven into saturation and thereby the storage time is eliminated.
Description : Define combinational logic
Last Answer : When logic gates are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved, the resulting circuit is called combinational logic.
Description : Karnaugh map is used for the purpose of (A) Reducing the electronic circuits used. (B) To map the given Boolean logic function. (C) To minimize the terms in a Boolean expression. (D) To maximize the terms of a given a Boolean expression.
Last Answer : (C) To minimize the terms in a Boolean expression.
Description : The logic 0 level of a CMOS logic device is approximately (A) 1.2 volts (B) 0.4 volts (C) 5 volts (D) 0 volts
Last Answer : Ans: D CMOS logic low level is 0 volts approx.
Description : Why totem pole outputs cannot be connected together.
Last Answer : Totem pole outputs cannot be connected together because such a connection might produce excessive current and may result in damage to the devices.
Description : For JK flipflop J = 0, K=1, the output after clock pulse will be (A) 1. (B) no change. (C) 0. (D) high impedance.
Last Answer : Ans: C J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So whatever be the previous output, the next state will be 0.
Description : The output of a JK flipflop with asynchronous preset and clear inputs is 1'. The output can be changed to 0' with one of the following conditions. (A) By applying J = 0, K = 0 and using a clock. (B) ... (C) By applying J = 1, K = 1 and using the clock. (D) By applying a synchronous preset input.
Last Answer : Ans: C Preset state of JK Flip-Flop =1 With J=1 K=1 and the clock next state will be complement of the present state.
Description : The output of SR flip flop when S=1, R=0 is (A) 1 (B) 0 (C) No change (D) High impedance
Last Answer : Ans: A As for the SR flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.
Description : For JK flip flop with J=1, K=0, the output after clock pulse will be (A) 0. (B) 1. (C) high impedance. (D) no change.
Last Answer : (B) 1.
Description : When the set of input data to an even parity generator is 0111, the output will be (A) 1 (B) 0 (C) Unpredictable (D) Depends on the previous input
Last Answer : Ans: B In even parity generator if number of 1 is odd then output will be zero.
Description : In successive-approximation A/D converter, offset voltage equal to 1/2 LSB is added to the D/A converter's output. This is done to (A) Improve the speed of operation. (B) Reduce the maximum ... Increase the number of bits at the output. (D) Increase the range of input voltage that can be converted
Last Answer : (B) Reduce the maximum quantization error.
Description : If the input to T-flipflop is 100 Hz signal, the final output of the three T-flipflops in cascade is (A) 1000 Hz (B) 500 Hz (C) 333 Hz (D) 12.5 Hz.
Last Answer : (D) 12.5 Hz.
Description : In what state must the inputs to a NOR gate be in order to produce a logic 1 output?
Last Answer : All inputs must be low.
Description : What are the advantages of TTL (transistor transistor logic)?
Last Answer : To know about the advantages of TTL logic family, one should have a basic idea about RTL, DTL etc. Diode logic (DL) uses diodes to implement logical functions like AND and OR. But the disadvantage is that it can ... delay offered by them, the logic levels may sometimes change i. e. 0 t0 1 or 1 to 0.
Description : What are the types of TTL logic?
Last Answer : 1. Open collector output 2. Totem-Pole Output 3. Tri-state output.
Description : TTL logic family is most popularly used industries because it 1.provides greater operating speed 2.has a good fan in & fan out 3.has easy interface with other digital circuitry 4.all the above
Last Answer : It is a basically a bipolar circuit which has TTL band hate fan fan out
Description : What values are found in the output of the logic gate ?
Last Answer : 0 or 1 value is found in the output of the logic gate .
Description : In a logic circuit the NOR and NAND gate functions ____________. A. must be accomplished with a common base transistor arrangement B. are available in diode form C. are exact opposites with the ... . have output conditions that are exact opposites to the output condition for OR and AND, respectively
Description : A two-input X-OR gate will produce a HIGH output when the inputs are at what logic levels?
Last Answer : . One or the other of the inputs must be HIGH, but not both at the same time.
Description : A NAND gate has inputs labeled as A, B, and C. If A and B are HIGH, C must be at what logic level to produce a HIGH output?
Last Answer : . Low.
Description : A NAND gate has Z and X as inputs. What will be the output logic level if Z is HIGH and X is LOW?
Last Answer : HIGH.
Description : The output of logic gate is '1' when all its inputs are at logic '0' The gate is (A) NAND/EX-OR (B) NOR/EX-OR (C) AND/EX-NOR (D) NOR/EX-NOR
Last Answer : The answer is (D) If we take two input A and B, and corresponding output Y then for nor gate Y = complement of (A+B) ;for ex-nor gate Y= A.B + complement of(A.B) The above two relation showing always Y =1 for A=0,B=0.
Description : The basic logic gate whose output is the complement of the input is the: - a) OR gate b) AND gate c) inverter d) comparator
Last Answer : The basic logic gate whose output is the complement of the input is the: - inverter
Last Answer : A Gate is a logic circuit with one or more inputs, but only One output
Description : What Is Tri-state Logic?
Last Answer : Answer :Three Logic Levels are used and they are High, Low, High impedance state. The high and low are normal logic levels & high impedance state is electrical open circuit conditions. Tri-state logic has a third line called enable line.