Description : What is the Address (SFR) for TCON, SCON, SBUF, PCON and PSW respectively? a) 88H, 98H, 99H, 87H, 0D0H. b) 98H, 99H, 87H, 88H, 0D0H c) 0D0H, 87H, 88H, 99H, 98H d) 87H, 88H, 0D0H, 98H, 99H
Last Answer : c) 0D0H, 87H, 88H, 99H, 98H
Description : In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor communication and is of ____ bit address. a) SM1, 9EH b) TB8 , 9CH c) SM2 , 9DH d) SM0, 9FH
Last Answer : c) SM2 , 9DH
Description : What is the address range of SFR Register bank? a) 00H-77H b) 40H-80H c) 80H-7FH d) 80H-FFH
Last Answer : c) 80H-7FH
Last Answer : d) 80H-FFH
Description : Which of the following is of bit operations? i) SP ii) P2 iii) TMOD iv) SBUF v) IP a) ii, v only b) ii, iv, v only c) i, v only d) iii, ii only
Last Answer : c) i, v only
Last Answer : a) ii, v only
Description : Which of the following statements on DRAM are correct? i) Page mode read operation is faster than RAS read. ii) RAS input remains active during column address strobe. iii) The row and column addresses are strobed into the ... RAS and CAS inputs respectively. a) i & iii b) i & ii c) all d) iii
Last Answer : d) iii
Description : Draw the format of TCON register of 8051 and describe the function of each bit of it.
Last Answer : TCON: TIMER/COUNTER CONTROL REGISTER.BIT ADDRESSABLE TF1 TCON. 7 Timer 1 overflows flag. Set by hardware when the Timer/Counter 1 Overflows. Cleared by hardware as processor ... 0 type control bit. Set/cleared by software to Specify falling edge/low level triggered External Interrupt
Description : PSW stands for (1) Program status word (2) Processor status word (3) Process status word (4) Primitive status word
Last Answer : Program status word
Description : Draw the format of PSW register of 8051 microcontroller and explain the function of each bit.
Last Answer : 1. CY: Carry flag. This flag is set whenever there is a carry out from the D7 bit after an 8 bit addition or subtraction. It can also be set to 1 or 0 directly by instructions such as SETB C and ... the A register contains an odd number of 1s, then P=1. P=0 if A has an even number of 1s.
Description : Draw the format of SCON register.
Last Answer : SM0 SCON.7 Serial port mode specifier SM1 SCON.6 Serial port mode specifier SM2 SCON.5 Used for multiprocessor communication (Make it 0.) REN SCON.4 Set/ cleared by software to enable/ ... flag. Set by hardware halfway through the stop bit time in mode 1. Must be cleared by software.
Description : Describe serial communication in 8051. Explain the use of SCON register.
Last Answer : 8051 micro controller communicate with another peripheral device through RXD and TXD pin of port3.controller have four mode of serial communication. 1. Serial Data Mode-0 (Baud Rate Fixed) In this mode ... .0 Receive interrupt flag. Set by hardware halfway through the stop bit time in mode 1.
Description : Describe power down mode and ideal mode of 8051 with circuit diagram . which SFR is used to set these modes and draw the same.
Last Answer : IDLE MODE In the Idle mode, the internal clock signal is gated off to the CPU, but not to the Interrupt, Timer and Serial Port functions. The CPU status is preserved in its entirety, the Stack Pointer, ... t change on chip RAM PCON (Power Control Register) SFR is used to set these modes.
Description : List SFR in 8051.
Last Answer : ACC and B registers - 8 bit each DPTR : [DPH:DPL] - 16 bit combined PC : Program Counter - 16 bits Stack pointer SP - 8 bit PSW : Program Status Word Port Latches ... , serial control Timer Registers (TCON,TMOD,TL0/1,TH0/1) Power control Interrupt Enable, Interrupt Priority
Description : Interfacing devices for DMA controller, programmable interval timer are respectively…a) 8257, 8253 b) 8253, 8257 c) 8257,8251 d)8251,825721.
Last Answer : a) 8257, 8253
Description : How many synchronous and asynchronous modes are there in serial port of 8096? M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/1 Microprocessors and Microcontrollers/ Multiple Choice Questions Architecture of Micro ... 2, 2 respectively b) 3,1 respectively c) 1, 3 respectively d) 1, 2 respectively
Last Answer : c) 1, 3 respectively
Description : How many address lines in a 4096 x 8 EPROM CHIP?
Last Answer : 12 address lines.
Description : Pentium Pro can address _____ of memory: a. 4 GB b. 128 GB c. 256 GB d. 512 GB
Last Answer : a. 4 GB
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : When the RET instruction at the end of subroutine is executed, a. the information where the stack is iniatialized is transferred to the stack pointer b. the memory address of the RET instruction is ... two data bytes stored in the top two locations of the stack are transferred to the stack pointer
Last Answer : c. two data bytes stored in the top two locations of the stack are transferred to the program counter
Description : Microprocessor 8085 can address location upto a. 32K b. 128K c. 64K d. 1M
Last Answer : c. 64K
Description : How many address lines are needed to address each memory locations in a 2048 x 4 memory chip? a. 10 b. 11 c. 8 d. 12
Last Answer : b. 11
Description : When a subroutine is called, the address of the instruction following the CALL instructions stored in/on the a. stack pointer b. accumulator c. program counter d. stack
Last Answer : d. stack
Description : A stack pointer is a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory. b. a register that decodes and executes 16-bit arithmetic expression. c. The first memory location where a subroutine address is stored. d. a register in which flag bits are stored
Last Answer : a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory.
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory Address Register b. Memory Data Register c. Instruction Register d. Program Register
Last Answer : d. Program Register
Description : If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory) a. doubles b. remains unchanged c. halves d. increases by 2^(address bits)/addressability
Last Answer : c. halves
Description : For a memory with a 16-bit address space, the addressability is a. 16 bits b. 8 bits c. 2^16 bits d. Cannot be determined
Last Answer : d. Cannot be determined
Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : Registers, which are partially visible to users and used to hold conditional, are known as a. PC b. Memory address registers c. General purpose register d. Flags
Last Answer : c. General purpose register
Description : How many address lines are needed to address each memory location in a 2048 x 4 memory chip? a. 10 b. 11 c. 8 d. 12
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory address register b. Memory data register c. Instruction register d. Program counter
Last Answer : d. Program counter
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address register b. Memory data register c. Instruction registers d. Program counter
Last Answer : c. Instruction registers
Description : A name or number used to identify a storage location is called a. A byte b. A record c. An address d. All of above
Last Answer : c. An address
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Last Answer : b. Address bus
Description : A memory that is capable of determining whether a given datum is contained in one of its address is a. ROM b. PROM c. CAM d. RAM
Last Answer : c. CAM
Description : A type of core store that has a lower access time than the devices used for working store in the same processor is known as a. Core memory b. Buffer c. Fast core d. Address register
Last Answer : d. Address register
Description : If in a computer, 16 bits are used to specify address in a RAM, the number of addresses will be a. 216 b. 65,536 c. 64K d. Any of the above
Last Answer : b. 65,536
Description : A storage area used to store data to a compensate for the difference in speed at which the different units can handle data is a. Memory b. Buffer c. Accumulator d. Address
Last Answer : b. Buffer
Description : Which of the following will happen when data is entered into a memory location? a. It will add to the content of the location b. It will change the address of the memory location c. It will erase the previous content d. It will not be fruitful if there is already some data at the location
Last Answer : c. It will erase the previous content
Description : Before a disk drive can access any sector record, a computer program has to provide the record’s disk address. What information does this address specify? a. Track number b. Sector number c. Surface number d. All of above
Last Answer : d. All of above
Description : Instructions and memory address are represented by a. Character code b. Binary codes c. Binary word d. Parity bit
Last Answer : b. Binary codes
Description : how many address lines are needed to address each machine location in a 2048 x 4 memory chip? a. 10 b. 11 c. 8 d. 12
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address registers b. Memory data registers c. Instruction register d. Program counter
Last Answer : c. Instruction register
Description : A name or number used to identify a storage location devices? a. A byte b. A record c. An address d. All of above
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : Which are the READ operation can in simple steps: a. Address b. Data c. Control d. All of these
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus