In which addressing the operand is actually present in instruction:
a. Immediate addressing
b. Direct addressing 9
Register addressing
a
None of these

1 Answer

Answer :

a. Immediate addressing

Related questions

Description : In which addressing the simplest addressing mode where an operand is fetched from memory is a. Immediate addressing b. Direct addressing c. Register addressing d. None of these

Last Answer : b. Direct addressing

Description : In which mode the main memory location holds the EA of the operand: a. Immediate addressing b. Direct addressing c. Register addressing d. Indirect addressing

Last Answer : d. Indirect addressing

Description : Which addressing is an extremely influential way of addressing: a. Displacement addressing b. Immediate addressing 9 Direct addressing a Register addressing

Last Answer : a. Displacement addressing

Description : In immediate addressing the operand is placed a. in the CPU register b. after OP code in the instruction c. in memory d. in stack

Last Answer : b. after OP code in the instruction

Description : In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these

Last Answer : Direct addressing

Description : The final addressing mode that we consider is a. Immediate addressing b. Direct addressing c. Register addressing d. Stack addressing

Last Answer : d. Stack addressing

Description : Which addressing offset can be the content of PC and also can be negative: a. Relative addressing b. Immediate addressing c. Direct addressing d. Register addressing

Last Answer : a. Relative addressing

Description : In which addressing mode the operand is given explicitly in the instruction? A. Absolute B. Immediate C. Indirect D. Direct

Last Answer : B. Immediate

Description : Which one of the following is not an addressing mode? (A) Register indirect (B) Auto increment (C) Relative indexed (D) Immediate operand

Last Answer : (C) Relative indexed

Description : Two important fields of an instruction are. a. Opcode b. Operand c. Only a d. Botha&b

Last Answer : d. Botha&b

Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Last Answer : b. Effective

Description : An instruction code must specify the address of the__. a. Opecode b. Operand c. Both d. None

Last Answer : b. Operand

Description : Which register holds the current instruction to be executed. a. Instruction register b. Program register 9 Control register a None of these

Last Answer : a. Instruction register

Description : In length instruction some programs wants a complex instruction set containing more instruction, more addressing modes and greater address rang, as in case of a. RISC b. CISC c. Both d. None

Last Answer : b. CISC

Description : The most common addressing techiniques employed by a CPU is a. immediate b. direct c. indirect d. register e. all of the above

Last Answer : e. all of the above

Description : The advantage of ............... is that it can reference memory without paying the price of having a full memory address in the instruction. (A) Direct addressing (B) Indexed addressing (C) Register addressing (D) Register Indirect addressing

Last Answer : (D) Register Indirect addressing

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Last Answer : c. Instruction register, incremented and next

Description : Which register holds the next instruction to be executed:

Last Answer : c. Program control register

Description : Acontrol memory is__ stored in some area of memory: a. Control instraction b. Memory instruction c. Register instruction d. None of these

Last Answer : a. Control instraction

Description : Opcode is the machine instruction obtained from decoding instruction stored in. a. Stack pointer b. Address pointer Cc. Instruction register d. Incrementer

Last Answer : Cc. Instruction register

Description : Which is the input of control unit: a. Master clock signal b. Instruction register c. Flags d. Control signals from bus e. Allof these

Last Answer : e. Allof these

Description : Which are contains one or more register that may be referenced by machine instruction: a. Input b. Output c. CPU d. ALU

Last Answer : c. CPU

Description : A basic instruction that can be interpreted by computer generally has ________ A. An operand and an address B. decoder and an accumulator C. Sequence register and decoder D. None of the Above

Last Answer : A. An operand and an address

Description : specify where to get the source and destination operands for the operation specified by the a. Operand fields and opcode b. Opcode and operand c. Source and destination d. Cpu and memory

Last Answer : a. Operand fields and opcode

Description : The operation is specified by a binary code known as the a. Operand code b. Opcode c. Source code d. — Allof these

Last Answer : b. Opcode

Description : Which operation use one operand or unary operations: a. Arithmetic b. Logical c. Both d. None

Last Answer : c. Both

Description : Which operation is used to shift the content of an operand to one or more bits to provide necessary variation: a. Logical and bit manipulation b. Shift manipulation c. Circular manipulation d. None of these

Last Answer : b. Shift manipulation

Description : List out any two instructions of following addressing modes: (i) Immediate addressing. (ii) Register addressing.

Last Answer : (i) Immediate addressing instructions: 1. MOV A, #36H 2. MOV DPTR, #27A2H (ii) Register addressing. 1. MOV A, R0 2. MOV R7, A

Description : ___in all digital systems actually performs addition that can handle only two number at a time: a Register b. circuit c digital d. — Allof these

Last Answer : b. circuit

Description : Content of the program counter is added to the address part of the instruction in order to obtain the effective address is called_______ A. relative address mode. B. index addressing mode. C. register mode. D. implied mode.

Last Answer : A. relative address mode.

Description : The ............... addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction. (A) Base indexed (B) Base indexed plus displacement (C) Indexed (D) Displacement

Last Answer : (D) Displacement

Description : The extent nesting in subroutine is limited only by: a. Number of available Stack locations b. Number of available Addressing locations c. Number of available CPU locations d. Number of available Memory locations

Last Answer : a. Number of available Stack locations

Description : ___ mode of addressing is a form of implied addressing: a. Stack b. Array Cc. Queue d. ‘Binary

Last Answer : a. Stack

Description : Write an example for immediate operand.

Last Answer : The quick add instruction with one constant operand is called add immediate or addi.To add 4 to register $s3, we just writeaddi $s3,$s3,4 # $s3 = $s3 + 4.

Description : Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes

Last Answer : . Critical sectio

Description : The complete set of op-codes for a particular microprocessor defines the_ set for that processor: a. Code b. Function c. Module d. Instruction

Last Answer : d. Instruction

Description : Which is the method by which instructions are selected for execution: a. Instruction selection b. — Selection control c. Instraction sequencing d. All of these

Last Answer : c. Instraction sequencing

Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Last Answer : a. The address of next instruction to be run

Description : As the instruction length increases ————_ of instruction addresses in all the instruction is_ a. Implicit inclusion b. Implicit and disadvantageous c. Explicit and disadvantageous d. Explicit and disadvantageous

Last Answer : c. Explicit and disadvantageous

Description : __is the sequence of operations performed by CPU in processing an instruction: a. Execute cycle b. Fetch cycle c. Decode d. Instruction cycle

Last Answer : d. Instruction cycle

Description : The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these

Last Answer : b. Execution time

Description : _is the step during which a new instruction is read from the memory: a Decode b. Fetch c. Execute d. None of these

Last Answer : b. Fetch

Description : is the step during which the operations specified by the instruction are executed: a. Execute b. Decode c. Both a& b d. None of these

Last Answer : a. Execute

Description : Decode is the step during which instruction is__ a. Initialized b. Incremented c. Decoded d. Bothb&c

Last Answer : c. Decoded

Description : The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Last Answer : b. Address

Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these

Last Answer : a. Operation

Description : Which are designed to interpret a specified number of instruction code. a. Programmer b. Processors c. Instruction d. Opcode

Last Answer : b. Processors

Description : __is divided into a number of fields and is represented as a sequence of bits: a. instruction b. — instruction set c. instruction code d. parity code

Last Answer : a. instruction

Description : Which unit is necessary for the execution of instruction: a. Timing b. Control ce. Both d. None of these

Last Answer : ce. Both