In length instruction some programs wants a complex instruction set containing more instruction, more
addressing modes and greater address rang, as in case of
a. RISC
b. CISC
c. Both
d. None

1 Answer

Answer :

b. CISC

Related questions

Description : In length instruction other programs on the other hand, want a small and fixed-size instruction set that contains only a limited number of opcodes, as in case of a. RISC b CISC c. Both d. None

Last Answer : a. RISC

Description : Which is a type of microprocessor that is designed with limited number of instructions: a. CISC b. RISC ce. Both d. None

Last Answer : ce. Both

Description : Which is a method of decomposing a sequential process into sub operations: a. Pipeline b. CISC c. RISC d. Database

Last Answer : a. Pipeline

Description : Which is not the main feature of DEC Alpha: a. 64 Bit RISC processor b. Designed to replace 32 VAX(CISC) c. Seven stage split integer/floating point pipeline d. Variable Instruction length

Last Answer : d. Variable Instruction length

Description : In post-indexing the contents of the address field are used to access a memory location containing a___ address: Immediate addressing Direct addressing Register addressing ao | None of these

Last Answer : Direct addressing

Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these

Last Answer : a. Pipeline

Description : Decoding of an instruction in RISC architecture means decision on working of control unit for: a. Remainder of instructions b. _ Divisor of instructions c. Dividend of instructions d. None of these

Last Answer : a. Remainder

Description : Assume a two address format specified as source, destination. Examine the following sequence of instruction and explain the addressing modes used and the operation done in every instruction?

Last Answer : 1. Move (R5) +, R0 2. Add (R5) +, R0. 3. Move (R0), (R5) 4. Move 16(R5), R3 5. Add #40, R5

Description : In which addressing the operand is actually present in instruction: a. Immediate addressing b. Direct addressing 9 Register addressing a None of these

Last Answer : a. Immediate addressing

Description : CISC stands for _________ A. Compound Instruction Set Computer B. Complex Information Set Computer C. Compound Information Set Computer D. Complex Instruction Set Computer

Last Answer : D. Complex Instruction Set Computer

Description : CISC stands for: a. Complex instruction set computer b. Camper instruct set of computer c. Compared instruction set computer d. None of these

Last Answer : a. Complex instruction set computer

Description : CISC stands for: a. Complex Instruction System Computer b. Complex Instruction Set Car c. Complex Instruction Set Computer d. None of these

Last Answer : c. Complex Instruction Set Computer

Description : The instruction set can have variable-length instruction format primarily due to: a. Varying number of operands b. Varying length of opcodes in some CPU ce. Both d. None

Last Answer : ce. Both

Description : The instruction set of RISC processor is A. Simple and lesser in number B. Complex and lesser in number C. Simple and larger in number D. Complex and larger in number

Last Answer : A. Simple and lesser in number 

Description : The length of instruction set depends on: a. Data size b. Memory size c. Both d. None

Last Answer : b. Memory size

Description : Which of the following is true about CISC processors? A. The instruction set is non-orthogonal B. The number of general purpose registers is limited C. Instructions are like macros in c language D. Variable length instructions E. All of these F. None of these

Last Answer : E. All of these 

Description : How many modes the address in control memory are divided. a 2 b 3 c. 5 d 7

Last Answer : a 2

Description : For CISC architecture___ controllers are better: a. Microprogrammed b. Hardwired c. Betterwired d. None of these

Last Answer : a. Microprogrammed

Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these

Last Answer : a. The address of next instruction to be run

Description : An instruction code must specify the address of the__. a. Opecode b. Operand c. Both d. None

Last Answer : b. Operand

Description : Which is the most important component of a digit computer that interprets the instruction and processes the data contained in computer programs: MU b. ALU c. CPU d. PC

Last Answer : c. CPU

Description : What is the difference between CISC and RISC?

Last Answer : RISC : Reduced Instruction Set Computer. A RISC system has a reduced number of instructions (making it easier to implement efficient optimizing compilers) and more importantly it is load store architecture where ... data in two memory locations. e.g. Intel Pentium (x86), DEC MicroVAX, Motorola 680x0

Description : Identify the correct statement A) IBM PCs used RISC CPU designs B) Macintosh used CISC CPU design C) IBM used CISC CPU design D) None of above is true

Last Answer : Answer : C

Description : Which are the architectural paradigms in microprocessor: a. RISC b. CISC c. PISC d. A and B

Last Answer : d. A and B

Description : Which is the architecture of microprocessor: a. CISC b. RISC c. All of these d. None of these

Last Answer : c. All of these

Description : What is the processor used by ARM7? A. 8-bit CISC B. 8-bit RISC C. 32-bit CISC D. 32-bit RISC

Last Answer : D. 32-bit RISC 

Description : The instruction fetch operation is initiated by loading the contents of program counter into the and sends _ request to memory: a. Memory register and read b. Memory register and write c. Data register and read d. Address register and read

Last Answer : d. Address register and read

Description : The contents of the program counter isthe __——__—oof the instruction to be run. a. Data b. Address c. Counter d. None of these

Last Answer : b. Address

Description : The instruction read from memory is then placed in the ___and contents of program counter is __ so that it contains the address of_ __ instruction in the program. a. Program counter, ... incremented and previous c. Instruction register, incremented and next d. Address register, decremented and next

Last Answer : c. Instruction register, incremented and next

Description : When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non ... , Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine

Last Answer : d. Executable, Stack and Subroutine

Description : Micro-orders generate the_ __ address of operand and execute instruction and prepare for fetching next instruction from the main memory: a. Physical b. Effective c. Logical d. all of above

Last Answer : b. Effective

Description : Opcode is the machine instruction obtained from decoding instruction stored in. a. Stack pointer b. Address pointer Cc. Instruction register d. Incrementer

Last Answer : Cc. Instruction register

Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU

Last Answer : b. Main memory

Description : Who change the address in the program counter and cause the flow of control to be altered: a Shift manipulation b. Circular manipulation c. Program control instruction d. __ Allof these

Last Answer : c. Program control instruction

Description : which are of the following modern assemblers: a. MIPS b. Sun SPARC c. HP PA-RISC d, x86(x64) e. all of these

Last Answer : e. all of these

Description : In RISC architecture access to registers is made as a block and register file in a particular register can be selected by using: a. Multiplexer b. Decoder c. Subtractor d. Adder

Last Answer : b. Decoder

Description : Abus organization for seven __ register: a. ALU b. RISC c. CPU d. MUX

Last Answer : c. CPU

Description : five bits of OPR select one of the operation inthe __ in control register. a. CPU b. RISC ec ALU d. MUX

Last Answer : ec ALU

Description : Ininstruction formats the information required by the _ for execution: a. ALU b. CPU Cc. RISC d. DATA

Last Answer : b. CPU

Description : 80386 support overall ___ addressing modes to facilitate efficient execution of higher level language programs. a) 9 b) 10 c) 11 d) 12

Last Answer : 11

Description : In program control the instruction is set for the statement in a: a. Parallel b. Sequence c. Both d. None

Last Answer : b. Sequence

Description : As the instruction length increases ————_ of instruction addresses in all the instruction is_ a. Implicit inclusion b. Implicit and disadvantageous c. Explicit and disadvantageous d. Explicit and disadvantageous

Last Answer : c. Explicit and disadvantageous

Description : The complete set of op-codes for a particular microprocessor defines the_ set for that processor: a. Code b. Function c. Module d. Instruction

Last Answer : d. Instruction

Description : __is divided into a number of fields and is represented as a sequence of bits: a. instruction b. — instruction set c. instruction code d. parity code

Last Answer : a. instruction

Description : Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these

Last Answer : a. Micro instructions

Description : One of use of microprogramming to implement _ ____ of processor in Intel 80x86 and Motorola 680x0 processors whose instruction set are evolved from 360 original. a. Control structure b. Without control c. Control unit d. Only control

Last Answer : c. Control unit

Description : In data transfer manipulation designing as instruction set for a system isa complex_ a. Art b. System Cc. Computer d. None of these

Last Answer : a. Art

Description : The extent nesting in subroutine is limited only by: a. Number of available Stack locations b. Number of available Addressing locations c. Number of available CPU locations d. Number of available Memory locations

Last Answer : a. Number of available Stack locations

Description : ___ mode of addressing is a form of implied addressing: a. Stack b. Array Cc. Queue d. ‘Binary

Last Answer : a. Stack

Description : In which addressing the simplest addressing mode where an operand is fetched from memory is a. Immediate addressing b. Direct addressing c. Register addressing d. None of these

Last Answer : b. Direct addressing