Description : Instruction formats contains the memory address of the a. Memory data b. Main memory Cc. CPU d. ALU
Last Answer : b. Main memory
Description : Abus organization for seven __ register: a. ALU b. RISC c. CPU d. MUX
Last Answer : c. CPU
Description : five bits of OPR select one of the operation inthe __ in control register. a. CPU b. RISC ec ALU d. MUX
Last Answer : ec ALU
Description : In memory transfer location address is supplied by that puts this on address bus. a. ALU b. CPU Cc. MAR d. MDR
Last Answer : b. CPU
Description : When subroutine is called contents of program counter is location address of __ instruction following call instruction is stored on _ __and program execution is transferred to __ address. a. Non ... , Stack and Main program Cc. Executable, Queue and Subroutine d. Executable, Stack and Subroutine
Last Answer : d. Executable, Stack and Subroutine
Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these
Last Answer : a. Pipeline
Description : Which is the most important component of a digit computer that interprets the instruction and processes the data contained in computer programs: MU b. ALU c. CPU d. PC
Description : Which are internal operations inside CPU: a. Data transfer b/w registers b. Instructing ALU to operate data c. Regulation of other internal operations d. All of these
Last Answer : d. All of these
Description : is just like a circular array: a. Data b. Register c. ALU d. CPU
Last Answer : b. Register
Description : Which is an important data transfer technique . a. CPU b. DMA Cc. CAD d. None of these
Last Answer : b. DMA
Description : How many bits of OPR select one of the operations in the ALU: a. 2 b 3 Cc. 4 dad 5
Last Answer : dad 5
Description : Decoding of an instruction in RISC architecture means decision on working of control unit for: a. Remainder of instructions b. _ Divisor of instructions c. Dividend of instructions d. None of these
Last Answer : a. Remainder
Description : In instruction formats instruction is represent by a___ _ of bits: a. Sequence b. Parallel c. Both d. None
Last Answer : a. Sequence
Description : sis given an instruction in machine language this instruction is fetched from the memory by the CPU to execute: a. ALU b. CPU c. MU d. All of these
Description : Which part work as a the brain of the computer and performs most of the calculation: a. MU b. PC c. ALU d. CPU
Last Answer : d. CPU
Description : function select takes op code in IR translating to function of ALU and it may be compact binary code or one line per ALU: a ALU b CPU c. Memory d. Cache
Last Answer : a ALU
Description : A stack in a digital computer isa partofthe_ ALU CPU a. b. c. Memory unit d None of these
Last Answer : c. Memory unit
Description : Which are contains one or more register that may be referenced by machine instruction: a. Input b. Output c. CPU d. ALU
Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these
Last Answer : b. Cache memory
Description : The register that includes the address of the memory unit is termed asthe _ a. MAR b PC Cc. IR d. None of these
Last Answer : a. MAR
Description : Register are assumed to use positive-edge-triggered _ a. Flip-flop b. Logics Cc. Circuit d. Operation
Last Answer : a. Flip-flop
Description : During program execution content of main memory undergo changes and, but control memory has _ microprogram: a. Static b. Dynamic c. Compile time d. Fixed
Last Answer : d. Fixed
Description : The function of these microinstructions is to issue the micro orders to_ _ a. CPU b. Memory c. Register d. Accumulator
Last Answer : a. CPU
Description : The section of the CPU that selects, interprects and monitors the execution of program instructions is (1) Memory (2) Register (3) Control unit (4) ALU
Last Answer : Control unit
Description : which are of the following modern assemblers: a. MIPS b. Sun SPARC c. HP PA-RISC d, x86(x64) e. all of these
Last Answer : e. all of these
Description : In RISC architecture access to registers is made as a block and register file in a particular register can be selected by using: a. Multiplexer b. Decoder c. Subtractor d. Adder
Last Answer : b. Decoder
Description : In length instruction some programs wants a complex instruction set containing more instruction, more addressing modes and greater address rang, as in case of a. RISC b. CISC c. Both d. None
Last Answer : b. CISC
Description : In length instruction other programs on the other hand, want a small and fixed-size instruction set that contains only a limited number of opcodes, as in case of a. RISC b CISC c. Both d. None
Last Answer : a. RISC
Description : Which is a type of microprocessor that is designed with limited number of instructions: a. CISC b. RISC ce. Both d. None
Last Answer : ce. Both
Description : Which is a method of decomposing a sequential process into sub operations: a. Pipeline b. CISC c. RISC d. Database
Description : __is data paths there is movement of data from one register to another or b/w ALU and a register. a. External b. Boreal c. Internal d. Exchange
Last Answer : c. Internal
Description : Outputs of instruction/data path in CU are. a. Reg R/W b. Load/Reg-Reg c. ALU function select d. Load control e. Read control f. IR Latch g. JUMP/Branch/Next PC h_ = All of these
Last Answer : h_ = All of these
Description : The time required to complete one instruction is called. a. Fetch time b. Execution time c. Control time d. All of these
Last Answer : b. Execution time
Description : In register transfer which system is a sequential logic system in which flip-flops and gates are constructed: a. Digital system b. Register Cc. Data d. None
Last Answer : a. Digital system
Description : In data transfer manipulation designing as instruction set for a system isa complex_ a. Art b. System Cc. Computer d. None of these
Last Answer : a. Art
Description : Which types of register holds a single vector containing at least two read ports and one write ports: a. Data system b. Data base Cc. Memory d. Vector register
Last Answer : d. Vector register
Description : Parallel computing means doing several takes simultaneously thus improving the performance of the a. Data system b. Computer system Cc. Memory d. Vector register
Last Answer : b. Computer system
Description : Copy of instruction in cache memory is known as: a Execution cache b. Data cache c. Instruction cache d. Allof these
Last Answer : c. Instruction cache
Description : Copy of data in cache memory is called. a. Datacache b. Execution cache c. Address cache d. Control cache
Last Answer : a. Datacache
Description : Before checking the program for errors in translating code into machine language the high level language code is loaded into __ a. Register b. Memory c. Data d. CPU
Last Answer : b. Memory
Description : Control memory is part of __ that has addressable storage registers and used as temporary storage for data. a. ROM b. RAM c. CPU d. Memory
Last Answer : b. RAM
Description : Which memory is used to copy instructions or data currently used by CPU: a. Main memory b. Secondary memory c. Cache memory d. None of these
Last Answer : c. Cache memory
Description : Which functions are performed by CU: a. Data exchange b/w CPU and memory or I/O modules b. External operations c. Internal operations inside CPU d Botha&c
Last Answer : d Botha&c
Description : ___is the data paths link CPU registers with memory or I/O modules. a. External data paths b. Internal data paths c. Boreal data paths d. Exchange data paths
Last Answer : a. External data paths
Description : In memory read the operation puts memory address on to a register known as : a. PC b. ALU ce. MAR d. — Allof these
Last Answer : ce. MAR
Description : In arithmetic operation numbers of register and the circuits for addition at a. ALU b. MAR c. Both d. None
Last Answer : a. ALU
Description : The variable of __ correspond to hardware register: a. RAM b. RIL c. ALU d. MAR
Last Answer : b. RIL
Description : emaphore provides mutual exclusion for accesses to the buffer pool and is initialized to the value: a. Mutex b. Mutual Cc. Memory d. __ Allof these
Last Answer : Mutex
Description : In which section only one process is allowed to access the shared variable and all other have to wait. a. Critical section b. Racing section Cc. Entry section d. Remainder section
Last Answer : . Critical section
Description : hich section is the remaining part of a process’s code: a. Racing section b. Critical section Cc. Entry section d. Reminder secti
Last Answer : b. Entry section