Description : In protocol each process can make a request onlyinan a. Increasing order b. Decreasing order c. Botha &b d. None of these
Last Answer : a. Increasing order
Description : Which state refers to a state that is not safe not necessarily a deadlocked state. a. Safe state b. Unsafe state c. Botha &b d. None of these
Last Answer : b. Unsafe state
Description : Which is one of the important I/O devices and is most commonly used as permanent storage device in any processor: a. Soft disk b. Hard disk c. Botha &b d. None of these
Last Answer : b. Hard disk
Description : which of the 2 files are created by the assembler. a. _ List and object file b. Link and object file c. Botha &b d. None of these
Last Answer : a. _ List and object file
Description : Ingiven lines of code MOV AX,BL have different type of operands according to assembler for 8086 architecture these identifiers must be of. a. Different type only in byte b. Same type either in word or byte c. Botha &b d. None of these
Last Answer : b. Same type either in word or byte
Description : IBM-360 type language is example which supporting _—___—sJanguage. a. Micro b. Macro c. Botha &b d. None of these
Last Answer : b. Macro
Description : address is not assigned by linker. a. Absolute b. Relative c. Botha &b a None of these
Last Answer : a. Absolute
Description : shave addresses where instructions are stored along with address of working storage: a. _ Relative entities b. Absolute entities c. Botha &b d. None of these
Last Answer : a. _ Relative entities
Description : Modern assemblers for RISC based architectures make optimization of instruction scheduling to make use of CPU __ efficiently: a. Pipeline b. Without pipeline c. Botha &b d. None of these
Last Answer : a. Pipeline
Description : Full form of MIPS assembler is: a. Microprocessor without interlocked pipeline stage b. Microprocessor with interlocked pipeline stage c. Botha &b d. None of these
Last Answer : a. Microprocessor without interlocked pipeline stage
Description : Ina complex program, the overlaps: a. Branching b. Condition c. Botha &b d. None of these
Last Answer : a. Branching
Description : Avoid crossing flow lines. a. Flowchart b. Algorithm c. Botha &b d. None of these
Last Answer : a. Flowchart
Description : is useful to prepare detailed program documentation: a. Flowchart b. Algorithm c. Botha &b d. None of these
Description : Cache memory is located between main memory and : a. CPU b. Memory c. Botha &b d. None of these
Last Answer : a. CPU
Description : Return instruction is written in_ to written to main program: a. Subroutine b. Main program c. Botha &b d. None of these
Last Answer : a. Subroutine
Description : subroutine declaration come after procedure announcement: a. Global b. Local c. Botha &b d. None of these
Last Answer : a. Global
Description : Callis_ subroutine call. a. Conditional b. Unconditi c. Botha &b d. None of these
Last Answer : b. Unconditi
Description : The processed data is sent for output to standard __ device which by default is computer screen: a. Input b. Output c. Botha &b d. None of these
Last Answer : b. Output
Description : Each instruction is executed by set of micro operations termed as. a. Micro instructions b. Mini instructions c. Botha &b d. None of these
Last Answer : a. Micro instructions
Description : Mode of addresses in control memory are: a. Executive mode b. Task mode c. Botha&b d. None of these
Last Answer : c. Botha&b
Description : The simplest method of controlling sequence of instruction execution is to have each instruction explicitly specify: a. The address of next instruction to be run b. Address of previous instruction c. Both a &b d. None of these
Last Answer : a. The address of next instruction to be run
Description : Execution of instruction specified by instruction to perform: a. Operation b. Operands c. Both a &b d. None of these
Last Answer : a. Operation
Description : Which memory is assembled between main memory and CPU: a. Primary memory b. Cache memory Cc. Botha & b d. None of these
Last Answer : b. Cache memory
Description : function is used to transfer the control to end of a program which uses one argument( ) and takes value is zero for_ __ termination and non-zero for _termination: a. _ Exit( ) normal, abnormal b. Break, normal, abnormal Botha & b None of these
Last Answer : a. _ Exit( ) normal, abnormal
Description : getchar :: IO char in this given function what is indicated by IO char: a. when getchar is invoked it returns a character b. when getchar is executed it returns a character c. botha & b d. none of these
Last Answer : a. when getchar is invoked it returns a character
Description : A computer having writable control memory is known as_ a. Static micro programmable b. Dynamic micro programmable c. Botha & b d. None of these
Last Answer : b. Dynamic micro programmable
Description : state keeps track of position related to execution of an instruction: a. Major b. Minor c. Botha & b d. None of these
Last Answer : a. Major
Description : It contains the stack for PC storage during subroutine calls and input/output interrupt services: a. Seven- level hardware b. Eight- level hardware
Last Answer : b. Eight- level hardware
Description : is an external hardware event which causes the CPU to interrupt the current instruction sequence: a. Input interrupt b. Output interrupt c. Both d. None of these
Last Answer : c. Both
Description : Which interrupt services save all the register and flags. a. Save interrupt b. Input/output interrupt c. Service interrupt d. All of these
Last Answer : b. Input/output interrupt
Description : IRET stand for. a. Interrupt enter b. Interrupt return c. Interrupt delete d. None of these
Last Answer : b. Interrupt return
Description : Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these
Last Answer : d. = Alllof these
Description : Which are the not causes of the interrupt: a. In any single device b. In processor poll devices c. Itis an external analogy to exception d. None of these
Last Answer : c. Itis an external analogy to exception
Description : Which are the causes of the interrupt: a. In any single device b. In processor poll devices c. In a device whose ID number is stored on the address bus d. Allof these
Last Answer : d. Allof these
Description : Which are the functioning of I/O interrupt: a. The processor organizes all the I/O operation for smooth functioning b. After completing the I/O operation the device interrupt the processor c. Both d. None of these
Last Answer : b. After completing the I/O operation the device interrupt the processor
Description : Loading is with the task of storage management of operating system and mostly preformed after assembly: a. Bound b. Expanded c. Overlaps d. All of these
Last Answer : a. Bound
Description : Itis the task of the __to locate externally defined symbols in programs, load them in to memory by placing their __ of symbols in calling program: a. Loader and name b. Linker and values c. Linker and name d. Loader and values
Last Answer : d. Loader and values
Description : Which of the following 2 task are performed to execute an instruction by MCU: a. Microinstruction execution b. Microinstruction sequencing c. Botha&b d. None of these
Description : ___ mode of addressing is a form of implied addressing: a. Stack b. Array Cc. Queue d. ‘Binary
Last Answer : a. Stack
Description : In which addressing the simplest addressing mode where an operand is fetched from memory is a. Immediate addressing b. Direct addressing c. Register addressing d. None of these
Last Answer : b. Direct addressing
Description : In which mode the main memory location holds the EA of the operand: a. Immediate addressing b. Direct addressing c. Register addressing d. Indirect addressing
Last Answer : d. Indirect addressing
Description : The final addressing mode that we consider is a. Immediate addressing b. Direct addressing c. Register addressing d. Stack addressing
Last Answer : d. Stack addressing
Description : In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU. a) CS, high b) A0, high c) IRQ, high d) STB, high
Last Answer : c) IRQ, high
Description : Mention The Steps In The Interrupt Driven Mode Of Data Transfer.?
Last Answer : Answer :The steps followed in this type of transfer are as follows: The peripheral device would request for an interrupt. The request acknowledgement for the transfer is issued at the end of ... coordinates by the ISS. Again the Interrupt system is enabled and the above steps are repeated.
Description : Ms. Juhi, works as an IT Executive in a health insurance company named 'Total Health'. She has been assigned a task to design -Technology
Last Answer : S. No.Control used toControl1CUSTOMER‟S NAMETextField2CUSTOMER‟S CITYComboBox3POLICY TYPE (Individual/Family)RadioButton4INCLUSIONS (Critical Illness/Accidental Coverage/Health Checkup/Others)CheckBox/ListBox
Description : Strategy is developed by the visionary Chief Executive in------- mode of Str.Management : A. Planning mode B. Adaptive mode C. Strategic mode D. Entrepreneurial mode
Last Answer : Entrepreneurial mode
Description : Virtual Mode Flag bit can be set using ____ instruction or any task switch operation only in the _____ mode a) IRET, Virtual b) POPF, Real c) IRET, protected d) POPF, protected
Last Answer : b) POPF, Real
Description : emaphore provides mutual exclusion for accesses to the buffer pool and is initialized to the value: a. Mutex b. Mutual Cc. Memory d. __ Allof these
Last Answer : Mutex
Description : Which section is basically a sequence of instruction with a clear indication of beginning and end for updating shared variables. a. Racing section b. Critical section c. d. Both None of thes
Last Answer : . Critical sectio