Which of the following 8085 microprocessor hardware interrupt has the lowest priority? (A) RST 6.5 (B) RST 7.5 (C) TRAP (D) INTR

Which of the following 8085 microprocessor hardware interrupt has the lowest priority? (A) RST 6.5 (B) RST 7.5 (C) TRAP (D) INTR 
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Answer: D
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Which interrupt has the highest priority? a) INTR b) TRAP c) RST6.5

Description : Which interrupt has the highest priority? a) INTR b) TRAP c) RST6.5

Last Answer : c) RST6.5

The RST 7 instruction in 8085 microprocessor is equivalent to: (A) CALL 0010 H (B) CALL 0034 H (C) CALL 0038 H (D) CALL 003C H

Description : The RST 7 instruction in 8085 microprocessor is equivalent to: (A) CALL 0010 H (B) CALL 0034 H (C) CALL 0038 H (D) CALL 003C H

Last Answer : (C) CALL 0038 H

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Description : What are software interrupts? a) RST 0 - 7 b) RST 5.5 - 7.5 c) INTR, TRAP

Last Answer : a) RST 0

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Last Answer : B. stty intr \^c

8085 microprocessor has ............. hardware interrupts. (A) 2 (B) 3 (C) 4 (D) 5

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List the four instructions which control the interrupt structure of the 8085 microprocessor.

Description : List the four instructions which control the interrupt structure of the 8085 microprocessor.

Last Answer : • DI ( Disable Interrupts ) • EI ( Enable Interrupts ) • RIM ( Read Interrupt Masks ) • SIM ( Set Interrupt Masks )

Match the following mechanisms for interrupting the execution of a process and their uses. i) Interrupt a) Call to an operating system function ii) Trap b) Reaction to an asynchronous external event iii) Supervisor Call c) Handling of a error or an exception condition A) i-a, ii-b, iii-c B) i-c, ii-a, iii-b C) i-b, ii-c, iii-a D) i-a, ii-c, iii-b

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Last Answer : C) i-b, ii-c, iii-a

In 8085 microprocessor, the digit 5 indicates that the microprocessor needs (1) -5 volts, +5 volts supply (2) +5 volts supply only (3) -5 volts supply only (4) 5 MHz clock

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Last Answer : Answer: 2

Which of the following in 8085 microprocessor performs HL = HL + DE ? (A) DAD D (B) DAD H (C) DAD B (D) DAD SP

Description : Which of the following in 8085 microprocessor performs HL = HL + DE ? (A) DAD D (B) DAD H (C) DAD B (D) DAD SP

Last Answer : (A) DAD D

The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing 'SUB AL, BL' assembly language instruction, are (1) AL=0FH; CF=1; SF=1 (2) AL=F0H; CF=0; SF=0 (3) AL=F1H; CF=1; SF=1 (4) AL=1FH; CF=1; SF=1

Description : The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing 'SUB AL, BL' assembly language instruction, are ( ... ; CF=0; SF=0 (3) AL=F1H; CF=1; SF=1 (4) AL=1FH; CF=1; SF=1

Last Answer : Answer: 3

Explain Briefly What Happens When The Intr Signal Goes High In The 8085?

Description : Explain Briefly What Happens When The Intr Signal Goes High In The 8085?

Last Answer : Answer :The INTR is a maskable interrupt for the 8085. It has the lowest priority and is also non vectored. When this INTR signal goes into the high state the following things occur / ... the processor saves the address of new instruction into the STACK and an interrupt service subroutine begins.

What is the RST for the TRAP? a) RST5.5 b) RST4.5 c) RST4

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Last Answer : b) RST4.5

A scheduling Algorithm assigns priority proportional to the waiting time of a process. Every process starts with priority zero (lowest priority). The scheduler re-evaluates the process priority for every 'T' time units and decides next process to be scheduled. If the process have no I/O operations and all arrive at time zero, then the scheduler implements .............. criteria. (A) Priority scheduling (B) Round Robin Scheduling (C) Shortest Job First (D) FCFS

Description : A scheduling Algorithm assigns priority proportional to the waiting time of a process. Every process starts with priority zero (lowest priority). The scheduler re-evaluates the process priority for every 'T' time ... (A) Priority scheduling (B) Round Robin Scheduling (C) Shortest Job First (D) FCFS

Last Answer : (B) Round Robin Scheduling

Which of the following control fields in TCP header is used to specify the sender has no more data to transmit? (A) FIN (B) RST (C) SYN (D) PSH

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A job has four pages A, B, C, D and the main memory has two page frames only. The job needs to process its pages in following order: ABACABDBACD Assuming that a page interrupt occurs when a new page is brought in the main memory, irrespective of whether the page is swapped out or not. The number of page interrupts in FIFO and LRU page replacement algorithms are (A) 9 and 7 (B) 7 and 6 (C) 9 and 8 (D) 8 and 6

Description : A job has four pages A, B, C, D and the main memory has two page frames only. The job needs to process its pages in following order: ABACABDBACD Assuming that a page interrupt occurs when a new page is brought in the main ... replacement algorithms are (A) 9 and 7 (B) 7 and 6 (C) 9 and 8 (D) 8 and 6

Last Answer : (C) 9 and 8

What Are The Two Major Differences Between Intr And Other Interrupts ( Hardware)?

Description : What Are The Two Major Differences Between Intr And Other Interrupts ( Hardware)?

Last Answer : Answer :The two major differences between INTR and the other hardware interrupts are as follows:All the hardware interrupts are vectored interrupts but the INTR interrupt is not so. An INTR interrupt will ... saved but in the case of other hardware interrupts the locations is saved in the stack.

Which interrupt is not level sensitive in 8085? a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-trigging interrupt. c) a & b.

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Last Answer : b) RST7.5 is a raising edge-trigging interrupt.

In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1

Description : In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1

Last Answer : a)IE1

In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1

Description : In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1

Last Answer : c)IE0

Which Interrupt Has The Highest Priority?

Description : Which Interrupt Has The Highest Priority?

Last Answer : Answer :TRAP has the highest priority.

What is the vector location of TRAP interrupt?

Description : What is the vector location of TRAP interrupt? (A) 0000 h (B) 0008 h (C) 0014 h (D) 0024 h

Last Answer : What is the vector location of TRAP interrupt?  0024 h

How many speed of 8088,8085,8086 microprocessor: a. 2.5 Million instruction per second b. 1.5 Million instruction per second c. 3.5 Million instruction per second d. 1.6 Million instruction per second

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Last Answer : a. 2.5 Million instruction per second

Explain priority interrupts of 8085.

Description : Explain priority interrupts of 8085.

Last Answer : The 8085 microprocessor has five interrupt inputs. They are TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. These interrupts have a fixed priority of interrupt service. If two or more interrupts go ... 8085 is shown in the table. Interrupts Priority TRAP RST 7.5 RST 6.5 RST 5.5 INTR

Explain Briefly The Trap Input For The 8085.?

Description : Explain Briefly The Trap Input For The 8085.?

Last Answer : Answer :The TRAP input is sensitive to both edge and level. The pulse width for this signal should be in excess as compared to the normal noise width. A second trap will never be able to ... to low transition. The pulse widths are wider than normal widths so as to prevent unwanted false triggers.

In 8085, whenever a signal is received at TRAP terminal, its program execution is transferred to a subroutine

Description : In 8085, whenever a signal is received at TRAP terminal, its program execution is transferred to a subroutine on address A) 0000 H B) 002C H C) 0024 H D) 0004 H

Last Answer : In 8085, whenever a signal is received at TRAP terminal, its program execution is transferred to a subroutine on address 0024 H

Interrupt which arises from illegal or erroneous use of an instruction or data is (A) Software interrupt (B) Internal interrupt (C) External interrupt (D) All of the above

Description : Interrupt which arises from illegal or erroneous use of an instruction or data is (A) Software interrupt (B) Internal interrupt (C) External interrupt (D) All of the above

Last Answer : (B) Internal interrupt

A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register at the end of the fetch cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval

Description : A CPU handles interrupt by executing interrupt service subroutine................. (A) by checking interrupt register after execution of each instruction (B) by checking interrupt register ... cycle (C) whenever an interrupt is registered (D) by checking interrupt register at regular time interval

Last Answer : (A) by checking interrupt register after execution of each instruction

System calls are usually invoked by using: (A) A privileged instruction (B) An indirect jump (C) A software interrupt (D) Polling

Description : System calls are usually invoked by using: (A) A privileged instruction (B) An indirect jump (C) A software interrupt (D) Polling

Last Answer : (C) A software interrupt

The Register that stores all interrupt requests is: (A) Interrupt mask register (B) Interrupt service register (C) Interrupt request register (D) Status register

Description : The Register that stores all interrupt requests is: (A) Interrupt mask register (B) Interrupt service register (C) Interrupt request register (D) Status register

Last Answer : (C) Interrupt request register

Which of the following is an interrupt according to temporal relationship with system clock? (1) Maskable interrupt (2) Periodic interrupt (3) Division by zero (4) Synchronous interrupt

Description : Which of the following is an interrupt according to temporal relationship with system clock? (1) Maskable interrupt (2) Periodic interrupt (3) Division by zero (4) Synchronous interrupt

Last Answer : Answer: 4

Why interrupt masking is needed of microprocessor?

Description : Why interrupt masking is needed of microprocessor?

Last Answer : Need answer

8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s are in master slave configuration the number of interrupts available to the 8086 microprocessor is a) 8 b) 16 c) 15 d) 64

Description : 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s are in master slave configuration the number of interrupts available to the 8086 microprocessor is a) 8 b) 16 c) 15 d) 64

Last Answer : a) 8

In a microprocessor the service routine for a certain interrupt starts from a fixed location of memory which

Description : In a microprocessor the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set but the interrupt can be delayed or rejected. Such an interrupt is 

Last Answer : In a microprocessor the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set but the interrupt can be delayed or rejected. Such an interrupt is Maskable and vectored

The content of the accumulator after the execution of the following 8085 assembly language program, is: MVI A, 42H MVI B, 05H UGC: ADD B DCR B JNZ UGC ADI 25H HLT (A) 82 H (B) 78 H (C) 76 H (D) 47 H

Description : The content of the accumulator after the execution of the following 8085 assembly language program, is: MVI A, 42H  MVI B, 05H UGC: ADD B DCR B JNZ UGC ADI 25H HLT (A) 82 H (B) 78 H (C) 76 H (D) 47 H

Last Answer : (C) 76 H

The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B (A) 00H (B) 35H (C) EFH (D) 2FH

Description : The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B (A) 00H (B) 35H (C) EFH (D) 2FH

Last Answer : (D) 2FH

In 8085, which of the following performs: load register pair immediate operation? (1) LDAX rp (2) LHLD addr (3) LXI rp, data (4) INX rp

Description : In 8085, which of the following performs: load register pair immediate operation? (1) LDAX rp (2) LHLD addr (3) LXI rp, data (4) INX rp

Last Answer : Answer: 3

What is Microprocessor 8085?

Description : What is Microprocessor 8085?

Last Answer : 8085 is a 8 bit microprocessor designed by Intel.

What is the microprocessor - 8085 architecture?

Description : What is the microprocessor - 8085 architecture?

Last Answer : 8085 Architecture - II Written by: shankar â⠬¢ Edited by: KennethSleightPublished Sep 30, 2009 â⠬¢ Related Guides: IntelLearn in detail about the functions and working of flags, the timing ... ALU alone cannot successfully process a data and provide the result to the programmer. There are

How many operations are there in the instruction set of 8085 microprocessor?

Description : How many operations are there in the instruction set of 8085 microprocessor?

Last Answer : There are 74 operations in the 8085 microprocessor.

List the 16 – bit registers of 8085 microprocessor.

Description : List the 16 – bit registers of 8085 microprocessor.

Last Answer : Stack pointer (SP) and Program counter (PC).

What is Microprocessor? Give the power supply & clock frequency of 8085

Description : What is Microprocessor? Give the power supply & clock frequency of 8085

Last Answer : A microprocessor is a multipurpose, programmable logic device that reads binary instructions from a storage device called memory accepts binary data as input and processes data according ... provides result as output. The power supply of 8085 is +5V and clock frequency in 3MHz.

The stack pointer in the 8085 microprocessor is a: a) 16 bit register that points to stack memory locations b) 16 bit accumulator c) Memory location in the stack d) None of The Above

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Last Answer : a) 16 bit register that points to stack memory locations

What type of architecture is used in 8085 microprocessor?

Description : What type of architecture is used in 8085 microprocessor?

Last Answer : Ans- INTEL 8085 is a 8-bit microprocessor. It's based on Von-Neumann architecture in which the data and instructions are in the same memory space without any distinction between them. Data line: 8-bits--Can ... of data at a time. Address line: 16-bits--Can address upto 2^16(64KB) of address space.

What is function of ALE in 8085 microprocessor?

Description : What is function of ALE in 8085 microprocessor?

Last Answer : Ans-AlE stands for the address latch enableit 's working is that it differentiate the address and data bus in microprocessor.when it is high it select address bus .when it is low it select data bus.

Which is 16 Bit microprocessor: a. 8088 b. 8086 c. 8085 d. All of these

Description : Which is 16 Bit microprocessor: a. 8088 b. 8086 c. 8085 d. All of these

Last Answer : d. All of these

The___ was very successful in the calculator market at that time: a. Motorola 6800 and 6809 b. Microprocessor 4004 c. Intel 8085 d. None of these

Description : The___ was very successful in the calculator market at that time: a. Motorola 6800 and 6809 b. Microprocessor 4004 c. Intel 8085 d. None of these

Last Answer : b. Microprocessor 4004

Microprocessor 8085 can address location upto a. 32K b. 128K c. 64K d. 1M

Description : Microprocessor 8085 can address location upto a. 32K b. 128K c. 64K d. 1M

Last Answer : c. 64K

To put the 8085 microprocessor in the wait state(i) lower the-HOLD input (ii) lower the READY input (iii) raise the HOLD input(iv) raise the READY input

Description : To put the 8085 microprocessor in the wait state(i) lower the-HOLD input (ii) lower the READY input (iii) raise the HOLD input(iv) raise the READY input

Last Answer : (ii) lower the READY input

In an 8085 microprocessor, the instruction CMP B has been executed while the contentsof accumulator is less than that of register B. As a result carry flag and zero flag will berespectively (A) set, reset (B) reset, set (C) reset, reset (D) set, set

Description : In an 8085 microprocessor, the instruction CMP B has been executed while the contentsof accumulator is less than that of register B. As a result carry flag and zero flag will berespectively (A) set, reset (B) reset, set (C) reset, reset (D) set, set

Last Answer : (A) set, reset