Description : Which pin of port 3 is has an alternative function as write control signal for external data memory? a) P3.8 b) P3.3 c) P3.6 d) P3.1
Last Answer : d) P3.1
Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option ... b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : c) EA, high, external, internal
Description : If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM together with _____ memory and devices. a) EA, high, internal, external b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : a) EA, high, internal, external
Description : The external device is connected to a pin called the ______ pin on the processor chip. a. Interrupt b. Transfer c. Both d. None of these
Last Answer : a. Interrupt
Description : In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____. a) 000BH, a high to low transition on pin INT1 b) 001BH, a low to high transition on pin INT1 c) 0013H, a high to low transition on pin INT1 d) 0023H, a low to high transition on pin INT1
Last Answer : a) 000BH, a high to low transition on pin INT1
Description : The ALU of a computer responds to the commands coming from a. Primary memory b. Control section c. External memory d. Cache memory
Last Answer : b. Control section
Description : A___ on this pin indicates a memory operation: a. Low b. High c. Medium d. None of these
Last Answer : a. Low
Description : The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these
Last Answer : a. Read
Description : standard I/O uses which control pin on the micro processor: a. IO/M
Last Answer : a. IO/M
Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : Which is not the control bus signal: a. READ b. WRITE c. RESET
Last Answer : c. RESET
Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B
Last Answer : b. Write
Description : The two major types of computer chips are a. External memory chip b. Primary memory chip c. Microprocessor chip d. Both b and c
Last Answer : d. Both b and c
Description : In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C. a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2
Last Answer : a) 3, Mode2
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : The upper red arrow show that CPU sends out the control signals____ and _____ indicate the data is read from the memory: a. Memory request b. Read c. Both A and B d. None of these
Last Answer : c. Both A and B
Description : BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA
Last Answer : b) Odd bank memory
Description : When memory write or I/O read are active data is from the processor: a. Input b. Output c. Processor d. None of these
Last Answer : b. Output
Description : The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register
Last Answer : The microprocessor can read/write 16 bit data from or to memory
Description : In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller
Last Answer : a) 1, 8bit, single processor
Last Answer : c) 2, 9 bit, multiple processors
Description : 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv
Last Answer : c) 4, i,ii,iii
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : In ADC 0808 if _______ pin high enables output. a) EOC b) I/P0-I/P7 c) SOC d) OE
Last Answer : b) I/P0-I/P7
Description : SOD pin can drive a D flip-flop? a) SOD cannot drive any flip-flops. b) SOD cannot drive D flip-flop, but can drive any other flop-flops. c) Yes, SOD can drive D flop-flop. d) No, SOD cannot drive any other flop-flops except D flop-flop
Last Answer : b) SOD cannot drive D flip-flop, but can drive any other flop-flops
Description : What is the function of watchdog timer? a) The watchdog Timer is an external timer that resets the system if the software fails to operate properly. b) The watchdog Timer is an internal timer ... internal timer that resets the system if the software fails to operate properly. d) None of them
Last Answer : b) The watchdog Timer is an internal timer that sets the system if the software fails to operate properly.
Last Answer : c) The watchdog Timer is an internal timer that resets the system if the software fails to operate properly.
Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these
Last Answer : a. DMA acknowledge signal
Description : Which statement is false about WR signal: a. WR signal controls the input buffer b. The bar over WR means that this is an active low signal c. The bar over WR means that this is an active high signal d. If WR is 0 then the input data reaches the latch input
Last Answer : c. The bar over WR means that this is an active high signal
Description : What is the control unit's function in the CPU? a. To transfer data to primary storage b. to store program instruction c. to perform logic operations d. to decode program instruction
Last Answer : b. to store program instruction
Description : What is the function of IO/M signal in the 8085?
Last Answer : It is a status signal. It is used to differentiate between memory locations and I/O operations. When this signal is low (IO/M = 0) it denotes the memory related operations. When this signal is high (IO/M = 1) it denotes an I/O operation.
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : The brain of any computer system is a. ALU b. Memory c. CPU d. Control unit
Last Answer : c. CPU
Description : Which of the following terms is the most closely related to main memory? a. Non volatile b. Permanent c. Control unit d. Temporary
Last Answer : d. Temporary
Description : Which of the following are the two main components of the CPU? a. Control unit and registers b. Registers and main memory c. Control Unit and ALU d. ALU and bus
Last Answer : c. Control Unit and ALU
Description : A microprocessor retries instructions from : a. Control memory b. Cache memory c. Main memory d. Virtual memory
Last Answer : c. Main memory
Description : Serial port interrupt is generated, if ____ bits are seta) IE b) RI, IE c) IP, TI d) RI, TI
Last Answer : d) RI, TI
Description : Serial port vector address is of _______. And causes an interrupt when ________. a) 0013H, either TI or RI flag is set b) 0023H, either TI or RI flag is reset c) 0013H, either TI or RI flag is reset d) 0023H, either TI or RI flag is set
Last Answer : a) 0013H, either TI or RI flag is set
Description : Which of the following instruction is used to set bit port directly? a) SET P1.0 b) MOV P1.0, bit c) SETB P1.0 d) JB P1.0, bit
Last Answer : JB P1.0, bit
Description : Serial port interrupt is generated, if ____ bits are set a) IE b) RI, IE c) IP, TI d) RI, TI
Last Answer : a) IE
Description : How many synchronous and asynchronous modes are there in serial port of 8096? M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/1 Microprocessors and Microcontrollers/ Multiple Choice Questions Architecture of Micro ... 2, 2 respectively b) 3,1 respectively c) 1, 3 respectively d) 1, 2 respectively
Last Answer : c) 1, 3 respectively
Description : ___ memory system which is discussed later can improve matters in this respect: a. Data memory b. Cache memory c. Memory d. None of these
Last Answer : b. Cache memory
Description : Which is an integral part of any microcomputer system and its primary purpose is to hold program and data: a. Memory unit b. Register unit c. A and B d. None of these
Last Answer : a. Memory unit
Description : When the RET instruction at the end of subroutine is executed, a. the information where the stack is iniatialized is transferred to the stack pointer b. the memory address of the RET instruction is ... two data bytes stored in the top two locations of the stack are transferred to the stack pointer
Last Answer : c. two data bytes stored in the top two locations of the stack are transferred to the program counter
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory Address Register b. Memory Data Register c. Instruction Register d. Program Register
Last Answer : d. Program Register
Description : Where does a computer add and compare data? a. Hard disk b. Floppy disk c. CPU chip d. Memory chip
Last Answer : c. CPU chip
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory address register b. Memory data register c. Instruction register d. Program counter
Last Answer : d. Program counter
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address register b. Memory data register c. Instruction registers d. Program counter
Last Answer : c. Instruction registers