Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B
Last Answer : b. Write
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : c) bus width select
Last Answer : b) address valid strobe select
Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these
Last Answer : a. DMA acknowledge signal
Description : The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these
Last Answer : a. Read
Description : Which pin of port 3 is has an alternative function as write control signal for external data memory? a) P3.8 b) P3.3 c) P3.6 d) P3.1
Last Answer : d) P3.1
Last Answer : c) P3.6
Description : In 8051,After reset the SP register is initialized to address________. a. 8H b) 9H c) 7H
Last Answer : c) 7H
Description : In an 8085 microprocessor, the instruction CMP B has been executed while the contentsof accumulator is less than that of register B. As a result carry flag and zero flag will berespectively (A) set, reset (B) reset, set (C) reset, reset (D) set, set
Last Answer : (A) set, reset
Description : Serial port vector address is of _______. And causes an interrupt when ________. a) 0013H, either TI or RI flag is set b) 0023H, either TI or RI flag is reset c) 0013H, either TI or RI flag is reset d) 0023H, either TI or RI flag is set
Last Answer : a) 0013H, either TI or RI flag is set
Description : SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset. a) 2 byte, 08H b) 8 bit, 07H c) 1 byte, 09H d) 8 bit, 06H
Last Answer : d) 8 bit, 06H
Description : After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H
Description : ROM d) 8 bit, on chip 128 byte RAM. 3. After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : What type of control pins are needed in a microprocessor to regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time? a. Bus control b. Interrupts c. Bus arbitration d. Status
Last Answer : c. Bus arbitration
Description : Which of the following is used for manufacturing chips? a. Control bus b. Control unit c. Parity unit d. Semiconductor
Last Answer : d. Semiconductor
Description : Which is used for manufacturing chips? a. Bus b. Control unit c. Semiconductors d. A and b only
Last Answer : c. Semiconductors
Description : Which of the following are the two main components of the CPU? a. Control unit and registers b. Registers and main memory c. Control Unit and ALU d. ALU and bus
Last Answer : c. Control Unit and ALU
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus
Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus
Last Answer : b. Address bus
Description : The system is notified of a read or write operation by ___________ a) Appending an extra bit of the address b) Enabling the read or write bits of the devices c) Raising an appropriate interrupt signal d) Sending a special signal along the BUS
Last Answer : Sending a special signal along the BUS
Description : The upper red arrow show that CPU sends out the control signals____ and _____ indicate the data is read from the memory: a. Memory request b. Read c. Both A and B d. None of these
Last Answer : c. Both A and B
Description : Which are the READ operation can in simple steps: a. Address b. Data c. Control d. All of these
Description : Which is the components of computer: a. System Bus b. CPU c. Memory Unit d. All of these
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Description : Dot-matrix is a type of a. Tape e. Printer f. Disk g. Bus
Last Answer : e. Printer
Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these
Last Answer : a. CPU
Description : The information on the data bus is transferred to the ______register: a. MOC b. MDR c. VAM d. CPU
Last Answer : b. MDR
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit
Last Answer : b. 10 bit
Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64
Last Answer : b. 32
Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these
Last Answer : c. 65536
Description : Which Bus connects CPU & level 2 cache: a. Rear side bus b. Front side bus c. Memory side bus d. None of these
Last Answer : b. Front side bus
Description : The network of wires or electronic path ways on mother board back side: a. PCB b. BUS c. BOTH A and B d. None of these
Last Answer : c. BOTH A and B
Description : The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann
Last Answer : d. Von Neumann
Description : Which is called superhighway: a. Processor b. Multiplexer c. Backbone bus d. None of these
Last Answer : c. Backbone bus
Description : _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus
Last Answer : d. Bus
Description : To prevent another master from taking over the bus during a critical operation, the 486 can assert its _____signal. a) LOCK# or PLOCK# b) HOLD or BOFF c) HLDA d) HOLD
Last Answer : a) LOCK# or PLOCK#
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width
Last Answer : c) Address bus width
Description : Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.
Last Answer : a) Because 8085 processor has 8 bit ALU.
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus isĀ 20 bit
Description : A microporgram is sequencer perform the operation a. read b. write c. execute d. read and write e. read and execute
Last Answer : e. read and execute