Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64
Last Answer : b. 32
Description : 80386 support which type of descriptor table from the following? a) TDS b) ADS c) GDS d) MDS
Last Answer : c) GDS
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : 80386 support overall ___ addressing modes to facilitate efficient execution of higher level language programs. a) 9 b) 10 c) 11 d) 12
Last Answer : 11
Description : ____is used to control the cache with two new control bits not present in the 80386 microprocessor. What are the bits used to control the 8K byte cache? a) CR0, CD, NW b) CR0, NW, PWT c) Control Register Zero, PWT, PCD d) none
Last Answer : d) none
Description : The interrupt vector table of 80386 has been allocated ______ space starting from _______ to _______. a) 1Kbyte, 00000H, 003FFH b) 2Kbyte, 10000H, 004FFH c) 3Kbyte, 01000H, 007FFH d) 4Kbyte, 01000H, 009FFH
Last Answer : c) 3Kbyte, 01000H, 007FFH
Description : The ____ of can assembly line to be I/t p: a. Clock period b. Pipelining c. Throughput d. Flow through
Last Answer : c. Throughput
Description : The fetch-execute cycle is to use a system know as: a. Assembly line b. Pipelining c. Cache d. None of these
Last Answer : b. Pipelining
Description : Who is the represents the fundamental process in the operation of the CPU: a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these
Last Answer : a. The fetch-execute cycle and pipelining
Description : How can we make computers work faster? a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these
Description : Pipelining strategy is called implement a. instruction execution b. instruction prefetch c. instruction decoding d. instruction manipulation
Last Answer : b. instruction prefetch
Description : In 8086 microprocessor one of the following statements is not true.a)Coprocessor is interfaced in MAX mode b)Coprocessor is interfaced in MIN mode c)I/O can be interfaced in MAX / MIN moded)Supports pipelining
Last Answer : b)Coprocessor is interfaced in MIN mode
Description : Define pipelining.
Last Answer : Pipelining: Process of fetching the next instruction while the current instruction is executing is called pipelining which will reduce the execution time.
Description : In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____. a) 000BH, a high to low transition on pin INT1 b) 001BH, a low to high transition on pin INT1 c) 0013H, a high to low transition on pin INT1 d) 0023H, a low to high transition on pin INT1
Last Answer : a) 000BH, a high to low transition on pin INT1
Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option ... b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : c) EA, high, external, internal
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Last Answer : b. Address bus
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit
Last Answer : b. 10 bit
Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these
Last Answer : c. 65536
Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus
Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : c) bus width select
Last Answer : b) address valid strobe select
Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width
Last Answer : c) Address bus width
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus is 20 bit
Description : How many machine cycles does 8085 have, mention them
Last Answer : The 8085 have seven machine cycles. They are • Opcode fetch • Memory read • Memory write • I/O read • I/O write • Interrupt acknowledge • Bus idle
Description : The external device is connected to a pin called the ______ pin on the processor chip. a. Interrupt b. Transfer c. Both d. None of these
Last Answer : a. Interrupt
Description : A___ on this pin indicates a memory operation: a. Low b. High c. Medium d. None of these
Last Answer : a. Low
Description : standard I/O uses which control pin on the micro processor: a. IO/M
Last Answer : a. IO/M
Description : Which pin of port 3 is has an alternative function as write control signal for external data memory? a) P3.8 b) P3.3 c) P3.6 d) P3.1
Last Answer : d) P3.1
Description : In ADC 0808 if _______ pin high enables output. a) EOC b) I/P0-I/P7 c) SOC d) OE
Last Answer : b) I/P0-I/P7
Description : SOD pin can drive a D flip-flop? a) SOD cannot drive any flip-flops. b) SOD cannot drive D flip-flop, but can drive any other flop-flops. c) Yes, SOD can drive D flop-flop. d) No, SOD cannot drive any other flop-flops except D flop-flop
Last Answer : b) SOD cannot drive D flip-flop, but can drive any other flop-flops
Description : If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM together with _____ memory and devices. a) EA, high, internal, external b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : a) EA, high, internal, external
Last Answer : c) P3.6
Description : To prevent another master from taking over the bus during a critical operation, the 486 can assert its _____signal. a) LOCK# or PLOCK# b) HOLD or BOFF c) HLDA d) HOLD
Last Answer : a) LOCK# or PLOCK#
Description : A 20-bit address bus allows access to a memory of capacity (1) 1 Mb (2) 2 Mb (3) 32 Mb (4) 64 Mb
Last Answer : 1MB
Description : The use of spooler programs and/or …. Hardware allows personal computer operators to do the processing work at the same time a printing operation is in progress a. Registered mails b. Memory c. CPU d. Buffer
Last Answer : d. Buffer
Description : Which of the following memories allows simultaneous read and write operations? a. ROM b. RAM c. EPROM d. None of above
Last Answer : b. RAM
Description : Segmentation unit allows segments of _____ size at maximum. a) 4Gbytes b) 6Mbytes c) 4Mbytes d) 6Gbytes
Last Answer : a) 4Gbytes
Description : ACALL instruction allows specifying ______address in the instruction and calling subroutine within ______ program memory block. a) 2byte, 3K b) 11bit, 2K c) 9bit, 2K d) 1byte, 3K
Last Answer : c) 9bit, 2K
Description : Which of the following statements on DRAM are correct? i) Page mode read operation is faster than RAS read. ii) RAS input remains active during column address strobe. iii) The row and column addresses are strobed into the ... RAS and CAS inputs respectively. a) i & iii b) i & ii c) all d) iii
Last Answer : d) iii
Description : Which is the components of computer: a. System Bus b. CPU c. Memory Unit d. All of these
Description : What type of control pins are needed in a microprocessor to regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time? a. Bus control b. Interrupts c. Bus arbitration d. Status
Last Answer : c. Bus arbitration