Description : L2 cache memory is places at ______ a. On Processor b. On Mother Board c. On Memory d. All of these
Last Answer : b. On Mother Board
Description : L1 cache memory is places at ______ a. On Processor b. On Mother Board c. On Memory d. All of these
Last Answer : a. On Processor
Description : Which of the following memories has the shortest access times? a. Cache memory b. Magnetic bubble memory c. Magnetic core memory d. RAM
Last Answer : a. Cache memory
Description : The ALU of a computer responds to the commands coming from a. Primary memory b. Control section c. External memory d. Cache memory
Last Answer : b. Control section
Description : A microprocessor retries instructions from : a. Control memory b. Cache memory c. Main memory d. Virtual memory
Last Answer : c. Main memory
Description : Which Bus connects CPU & level 2 cache: a. Rear side bus b. Front side bus c. Memory side bus d. None of these
Last Answer : b. Front side bus
Description : The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these
Last Answer : a. Read
Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option ... b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : c) EA, high, external, internal
Description : If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM together with _____ memory and devices. a) EA, high, internal, external b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : a) EA, high, internal, external
Description : The ___ bit decides whether it is a system descriptor or code/data segment descriptor a) P b) S c) D d) G
Last Answer : a) P
Description : The fetch-execute cycle is to use a system know as: a. Assembly line b. Pipelining c. Cache d. None of these
Last Answer : b. Pipelining
Description : Pentium Pro Processor contains: a. L1 Cache b. L2 Cache c. Both L1 & L2 d. None of these
Last Answer : c. Both L1 & L2
Description : ____is used to control the cache with two new control bits not present in the 80386 microprocessor. What are the bits used to control the 8K byte cache? a) CR0, CD, NW b) CR0, NW, PWT c) Control Register Zero, PWT, PCD d) none
Last Answer : d) none
Description : The object of ‘Agenda’ is to inform– (A) About the profitability and activity (B) About the progress of company (C) About the matter in sequence to be discussed in the meeting (D) About the routine matters
Last Answer : Answer: About the matter in sequence to be discussed in the meeting
Description : For initial audits, additional matters the auditor may consider in the overall audit strategy and audit plan include the following except a. Major issues including the application of ... firm personnel with appropriate levels of capabilities and competence to respond to anticipated significant risks
Last Answer : Confirmation of material accounts receivable balance at the end of the year.
Description : The value memvar must be transferred to the ___: a. Computer b. CPU c. Both A and B d. None of these
Last Answer : b. CPU
Description : Which point to the ___ of the stack: a. TOP b. START c. MID
Last Answer : a. TOP
Description : 80386 support overall ___ addressing modes to facilitate efficient execution of higher level language programs. a) 9 b) 10 c) 11 d) 12
Last Answer : 11
Description : SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset. a) 2 byte, 08H b) 8 bit, 07H c) 1 byte, 09H d) 8 bit, 06H
Last Answer : d) 8 bit, 06H
Description : In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller
Last Answer : a) 1, 8bit, single processor
Description : 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv
Last Answer : c) 4, i,ii,iii
Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96
Last Answer : d) 16, MCS96
Description : The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,
Last Answer : a) 8 byte, on-chip 128 byte RAM.
Description : ___ Connection and the _______ instruction will solve the problem of synchronization between processor and coprocessor. a) INT & NMI, WAIT b) RQ/GT0 & RQ/GT1, FWAIT c) BUSY & TEST, FWAIT d) S0 & QS0, WAIT
Last Answer : b) RQ/GT0 & RQ/GT1, FWAIT
Description : In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU. a) CS, high b) A0, high c) IRQ, high d) STB, high
Last Answer : c) IRQ, high
Last Answer : c) 2, 9 bit, multiple processors
Description : Which is an integral part of any microcomputer system and its primary purpose is to hold program and data: a. Memory unit b. Register unit c. A and B d. None of these
Last Answer : a. Memory unit
Description : . An online backing storage system capable of storing larger quantities of data is a. CPU b. Memory c. Mass storage d. Secondary storage
Last Answer : c. Mass storage
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : When the RET instruction at the end of subroutine is executed, a. the information where the stack is iniatialized is transferred to the stack pointer b. the memory address of the RET instruction is ... two data bytes stored in the top two locations of the stack are transferred to the stack pointer
Last Answer : c. two data bytes stored in the top two locations of the stack are transferred to the program counter
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory Address Register b. Memory Data Register c. Instruction Register d. Program Register
Last Answer : d. Program Register
Description : Where does a computer add and compare data? a. Hard disk b. Floppy disk c. CPU chip d. Memory chip
Last Answer : c. CPU chip
Description : Which of the following registers is used to keep track of address of the memory location where the next instruction is located? a. Memory address register b. Memory data register c. Instruction register d. Program counter
Last Answer : d. Program counter
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address register b. Memory data register c. Instruction registers d. Program counter
Last Answer : c. Instruction registers
Description : Which computer memory is used for storing programs and data currently being processed by the CPU? a. Mass memory b. Internal memory c. Non-volatile memory d. PROM
Last Answer : b. Internal memory
Description : The magnetic storage chip used to provide non-volatile direct access storage of data and that have no moving parts are known as a. Magnetic core memory b. Magnetic tape memory c. Magnetic disk memory d. Magnetic bubble memory
Last Answer : a. Magnetic core memory
Description : A storage area used to store data to a compensate for the difference in speed at which the different units can handle data is a. Memory b. Buffer c. Accumulator d. Address
Last Answer : b. Buffer
Description : Which of the following will happen when data is entered into a memory location? a. It will add to the content of the location b. It will change the address of the memory location c. It will erase the previous content d. It will not be fruitful if there is already some data at the location
Last Answer : c. It will erase the previous content
Description : The act of retrieving existing data from memory is called a. Read-out b. Read from c. Read d. All of above
Last Answer : d. All of above
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address registers b. Memory data registers c. Instruction register d. Program counter
Last Answer : c. Instruction register
Description : CD-ROM stands for a. Compactable Read Only Memory b. Compact Data Read Only Memory c. Compactable Disk Read Only Memory d. Compact Disk Read Only Memory
Last Answer : d. Compact Disk Read Only Memory
Description : DMA stands for: a. Dynamic memory access b. Data memory access c. Direct memory access d. Both B and C
Last Answer : d. Both B and C
Description : DMA stands for: a. Direct memory access b. Direct memory allocation c. Data memory access d. Data memory allocation
Last Answer : a. Direct memory access
Description : The upper red arrow show that CPU sends out the control signals____ and _____ indicate the data is read from the memory: a. Memory request b. Read c. Both A and B d. None of these
Last Answer : c. Both A and B
Description : MDR stands for: a. Memory data register b. Memory data recode c. Micro data register d. None of these
Last Answer : a. Memory data register
Description : When memory write or I/O read are active data is from the processor: a. Input b. Output c. Processor d. None of these
Last Answer : b. Output
Description : When memory read or I/O read are active data is to the processor : a. Input b. Output c. Processor d. None of these
Last Answer : a. Input