Description : In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____. a) 000BH, a high to low transition on pin INT1 b) 001BH, a low to high transition on pin INT1 c) 0013H, a high to low transition on pin INT1 d) 0023H, a low to high transition on pin INT1
Last Answer : a) 000BH, a high to low transition on pin INT1
Description : If ______ and ________ connections are made so that an error condition in 8087 can interrupt to the processor. a) BHE, RQ/GT1 b) BUSY, TEST c) INT, NMI d) RQ/GT0, RQ/GT1
Last Answer : c) INT, NMI
Description : The DMA controllers are special hardware embedded into the chip in modern integrate processor that ____and_____ to the system; a. Data transfer b. arbitrate access c. Both A and B d. None of these
Last Answer : c. Both A and B
Description : _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus
Last Answer : d. Bus
Description : Which are the not causes of the interrupt: a. In any single device b. In processor poll devices c. Itis an external analogy to exception d. None of these
Last Answer : c. Itis an external analogy to exception
Description : standard I/O uses which control pin on the micro processor: a. IO/M
Last Answer : a. IO/M
Description : The interrupt vector table of 80386 has been allocated ______ space starting from _______ to _______. a) 1Kbyte, 00000H, 003FFH b) 2Kbyte, 10000H, 004FFH c) 3Kbyte, 01000H, 007FFH d) 4Kbyte, 01000H, 009FFH
Last Answer : c) 3Kbyte, 01000H, 007FFH
Description : RIM is used to check whether, ______ a) The write operation is done or not b) The interrupt is Masked or not c) a & b
Last Answer : b) The interrupt is Masked or not
Description : The two major types of computer chips are a. External memory chip b. Primary memory chip c. Microprocessor chip d. Both b and c
Last Answer : d. Both b and c
Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option ... b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : c) EA, high, external, internal
Description : Which pin of port 3 is has an alternative function as write control signal for external data memory? a) P3.8 b) P3.3 c) P3.6 d) P3.1
Last Answer : d) P3.1
Description : If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM together with _____ memory and devices. a) EA, high, internal, external b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : a) EA, high, internal, external
Last Answer : c) P3.6
Description : Which are the functioning of I/O interrupt: a. The processor organizes all the I/O operation for smooth functioning b. After completing the I/O operation the device interrupt the processor c. Both d. None of these
Last Answer : b. After completing the I/O operation the device interrupt the processor
Description : The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,
Last Answer : a) 8 byte, on-chip 128 byte RAM.
Description : An error in computer data is called a. Chip b. Bug c. CPU d. Storage device
Last Answer : b. Bug
Description : Which are benefit of input/output interrupt: a. It is an external analogy to exceptions b. The processor initiates and perform all I/O operation c. The data is transferred into the memory through interrupt handler d. = Alllof these
Last Answer : d. = Alllof these
Description : The growth of SSI up to____: a. 100 device on a chip b. 200 device on a chip c. 300 device on a chip d. 400 device on a chip
Last Answer : a. 100 device on a chip
Description : An integrated circuit is a. A complicated circuit b. An integrating device c. Much costlier than a single transistor d. Fabricated on a tiny silicon chip
Last Answer : d. Fabricated on a tiny silicon chip
Description : L2 cache memory is places at ______ a. On Processor b. On Mother Board c. On Memory d. All of these
Last Answer : b. On Mother Board
Description : L1 cache memory is places at ______ a. On Processor b. On Mother Board c. On Memory d. All of these
Last Answer : a. On Processor
Description : The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit
Last Answer : c) 40, 8 bit
Description : The coprocessors operate in ______ with a processor on the same buses and with the same instruction _______. a) Parallel, byte stream. b) Series, byte stream. c) Series, bite stream d) Parallel, bite stream.
Last Answer : a) Parallel, byte stream.
Description : The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit d) 40, 8 byte
Description : The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register
Last Answer : The microprocessor can read/write 16 bit data from or to memory
Description : Which are the causes of the interrupt: a. In any single device b. In processor poll devices c. In a device whose ID number is stored on the address bus d. Allof these
Last Answer : d. Allof these
Description : To overcome the lag in the operating speeds of the I/O device and the processor we use ___________ a) BUffer spaces b) Status flags c) Interrupt signals d) Exceptions
Last Answer : Status flags
Description : What is meant by interrupt?
Last Answer : Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine.
Description : List the four instructions which control the interrupt structure of the 8085 microprocessor.
Last Answer : • DI ( Disable Interrupts ) • EI ( Enable Interrupts ) • RIM ( Read Interrupt Masks ) • SIM ( Set Interrupt Masks )
Description : Serial port interrupt is generated, if ____ bits are seta) IE b) RI, IE c) IP, TI d) RI, TI
Last Answer : d) RI, TI
Description : Which are the flags of status register: a. Over flow flag b. Carry flag c. Half carry flag d. Zero flag e. Interrupt flag f. Negative flag g. All of these
Last Answer : g. All of these
Description : Serial port vector address is of _______. And causes an interrupt when ________. a) 0013H, either TI or RI flag is set b) 0023H, either TI or RI flag is reset c) 0013H, either TI or RI flag is reset d) 0023H, either TI or RI flag is set
Last Answer : a) 0013H, either TI or RI flag is set
Description : In 8096 we have _____interrupt sources and _______ interrupt vectors. a) 18, 8 b) 21, 6 c) 21, 8 d) 16, 8
Last Answer : c) 21, 8
Description : In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1
Last Answer : a)IE1
Description : Serial port interrupt is generated, if ____ bits are set a) IE b) RI, IE c) IP, TI d) RI, TI
Last Answer : a) IE
Description : 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s are in master slave configuration the number of interrupts available to the 8086 microprocessor is a) 8 b) 16 c) 15 d) 64
Last Answer : a) 8
Description : In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU. a) CS, high b) A0, high c) IRQ, high d) STB, high
Last Answer : c) IRQ, high
Last Answer : c) 21,
Last Answer : c)IE0
Description : What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that can be turned off by the programmer. c) none
Last Answer : b) An interrupt that can be turned off by the programmer.
Description : What is SIM? a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
Last Answer : c) Set Interrupt Mask.
Description : Which interrupt is not level sensitive in 8085? a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-trigging interrupt. c) a & b.
Last Answer : b) RST7.5 is a raising edge-trigging interrupt.
Description : Which interrupt has the highest priority? a) INTR b) TRAP c) RST6.5
Last Answer : c) RST6.5
Description : The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann
Last Answer : d. Von Neumann
Description : ______ input is available, so that another coprocessor can be connected and function in _________ with the 8087. . a) RQ/GT0, parallel b) RQ/GT1, parallel c) QS1 & QS0, parallel d) S0 & S1, parallel.
Last Answer : a) RQ/GT0, parallel
Description : Offline device is a. A device which is not connected to CPU b. A device which is connected to CPU c. A direct access storage device d. An I/O device
Last Answer : a. A device which is not connected to CPU