In 8279, the keyboard entries are debounced and stored in an _________, that is further accessed by the CPU to read the key codes. a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO

In 8279, the keyboard entries are debounced and stored in an _________, that is further accessed by the CPU to read the key codes.
a) 8-bit FIFO b) 8-byte FIFO
c) 16 byte FIFO
d) 16 bit FIFO
by

1 Answer

Answer :

b) 8-byte FIFO
by

Related questions

In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the ____. a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte d) LILO byte by byte.

Description : In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the ____. a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte d) LILO byte by byte.

Last Answer : a) FIFO byte by byte

The 8279 normally provides a maximum of _____ seven segment display interface with CPU. a) 8 b) 16 c) 32 d) 18

Description : The 8279 normally provides a maximum of _____ seven segment display interface with CPU. a) 8 b) 16 c) 32 d) 18

Last Answer : a) 8

In 8087, _______ many register stack are there? And of _____ registers. These registers are used as _________ stack. a) 7, 40 bit, FIFO. b) 8, 60 bit, LILO. c) 8, 80 bit, LIFO d) 7, 80 bit, FILO.

Description : In 8087, _______ many register stack are there? And of _____ registers. These registers are used as _________ stack. a) 7, 40 bit, FIFO. b) 8, 60 bit, LILO. c) 8, 80 bit, LIFO d) 7, 80 bit, FILO.

Last Answer : b) 8, 60 bit, LILO.

In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU. a) CS, high b) A0, high c) IRQ, high d) STB, high

Description : In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU. a) CS, high b) A0, high c) IRQ, high d) STB, high

Last Answer : c) IRQ, high

The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,

Description : The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,

Last Answer : a) 8 byte, on-chip 128 byte RAM.

In 8279 Status Word, data is read when ________ pins are low, and write to the display RAM with ____________ are low. a) A0, CS, RD & A0, WR, CS. b) CS, WR, A0 & A0, CS, RD c) A0, RD & WR, CS d) CS, RD & A0, CS.

Description : In 8279 Status Word, data is read when ________ pins are low, and write to the display RAM with ____________ are low. a) A0, CS, RD & A0, WR, CS. b) CS, WR, A0 & A0, CS, RD c) A0, RD & WR, CS d) CS, RD & A0, CS.

Last Answer : c) A0, RD & WR, CS

The original ASCII code used…bits of each byte, reserving that last bit for error checking a. 5 b. 6 c. 7 d. 8

Description : The original ASCII code used…bits of each byte, reserving that last bit for error checking a. 5 b. 6 c. 7 d. 8

Last Answer : c. 7

A 32 bit microprocessor has the word length equal to a. 2 byte b. 32 byte c. 4 byte d. 8 byte

Description : A 32 bit microprocessor has the word length equal to a. 2 byte b. 32 byte c. 4 byte d. 8 byte

Last Answer : c. 4 byte

SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset. a) 2 byte, 08H b) 8 bit, 07H c) 1 byte, 09H d) 8 bit, 06H

Description : SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset. a) 2 byte, 08H b) 8 bit, 07H c) 1 byte, 09H d) 8 bit, 06H

Last Answer : d) 8 bit, 06H

8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, register to register c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register

Description : 8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, register ... c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register

Last Answer : c) 232 byte, five 8bit, register to register

The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit

Description : The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit

Last Answer : c) 40, 8 bit

8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, register to register c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register

Description : 8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, ... c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register

Last Answer : d) 232 byte, six 8 bit, register to register

ROM d) 8 bit, on chip 128 byte RAM. 3. After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H

Description : ROM d) 8 bit, on chip 128 byte RAM. 3. After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H

Last Answer : c) 7H

The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit d) 40, 8 byte

Description : The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit d) 40, 8 byte

Last Answer : c) 40, 8 bit

A stack pointer is a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory. b. a register that decodes and executes 16-bit arithmetic expression. c. The first memory location where a subroutine address is stored. d. a register in which flag bits are stored

Description : A stack pointer is a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory. b. a register that decodes and executes 16-bit arithmetic expression. c. The first memory location where a subroutine address is stored. d. a register in which flag bits are stored

Last Answer : a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory.

The number of characters that can be stored in given physical space is a. Word length b. Byte c. Data density d. Field

Description : The number of characters that can be stored in given physical space is a. Word length b. Byte c. Data density d. Field

Last Answer : c. Data density

A byte consists of a. One bit b. Four bits c. Eight bits d. Sixteen bits

Description : A byte consists of a. One bit b. Four bits c. Eight bits d. Sixteen bits

Last Answer : c. Eight bits

The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register

Description : The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register

Last Answer : The microprocessor can read/write 16 bit data from or to memory 

How many bit stored by status register: a. 1 bit b. 4 bit c. 6 bit d. 8 bit

Description : How many bit stored by status register: a. 1 bit b. 4 bit c. 6 bit d. 8 bit

Last Answer : a. 1 bit

Because we wish to allow each ASCII code to occupy one location in memory, most memories are _____ addressable. a. BYTE b. NIBBLE c. WORD (16 bits) d. DOUBLEWORD (32 bits)

Description : Because we wish to allow each ASCII code to occupy one location in memory, most memories are _____ addressable. a. BYTE b. NIBBLE c. WORD (16 bits) d. DOUBLEWORD (32 bits)

Last Answer : a. BYTE

A UNIX file system has 1 KB block size and 4-byte disk addresses. What is the maximum file size if the inode contains ten direct block entries, one single indirect block entry, one double indirect block entry and one triple indirect block entry? (A) 30 GB (B) 64 GB (C) 16 GB (D) 1 GB

Description : A UNIX file system has 1 KB block size and 4-byte disk addresses. What is the maximum file size if the inode contains ten direct block entries, one single indirect block entry, one double indirect block entry and one triple indirect block entry? (A) 30 GB (B) 64 GB (C) 16 GB (D) 1 GB

Last Answer : (C) 16 GB

A unix file system has 1-KB blocks and 4-byte disk addresses. What is the maximum file size if i-nodes contain 10 direct entries and one single, double and triple indirect entry each? (A) 32 GB (B) 64 GB (C) 16 GB (D) 1 GB

Description : A unix file system has 1-KB blocks and 4-byte disk addresses. What is the maximum file size if i-nodes contain 10 direct entries and one single, double and triple indirect entry each? (A) 32 GB (B) 64 GB (C) 16 GB (D) 1 GB

Last Answer : (C) 16 GB

Stack words on: a. LILO b. LIFO c. FIFO d. None of these

Description : Stack words on: a. LILO b. LIFO c. FIFO d. None of these

Last Answer : b. LIFO

Which stack is used in 8085? a) FIFO b) LIFO c) FILO

Description : Which stack is used in 8085? a) FIFO b) LIFO c) FILO

Last Answer : b) LIFO

As compared to diskettes, the hard disks are a. More expensive b. More portable c. Less rigid d. Slowly accessed

Description : As compared to diskettes, the hard disks are a. More expensive b. More portable c. Less rigid d. Slowly accessed

Last Answer : a. More expensive

What is the size of memory which can be accessed by direct accessing in 8085 microprocessor?

Description : What is the size of memory which can be accessed by direct accessing in 8085 microprocessor? A) 64 kB B) 4 kB C) 128 kB D) 128 MB 

Last Answer : What is the size of memory which can be accessed by direct accessing in 8085 microprocessor? A) 64 kB B) 4 kB C) 128 kB D) 128 MB 

A technique used by codes to convert an analog signal into a digital bit stream is known as a. Pulse code modulation b. Pulse stretcher c. Query processing d. Queue management

Description : A technique used by codes to convert an analog signal into a digital bit stream is known as a. Pulse code modulation b. Pulse stretcher c. Query processing d. Queue management

Last Answer : a. Pulse code modulation

Instructions and memory address are represented by a. Character code b. Binary codes c. Binary word d. Parity bit

Description : Instructions and memory address are represented by a. Character code b. Binary codes c. Binary word d. Parity bit

Last Answer : b. Binary codes

Which processor provided 1 MB memory: a. 16-bit 8086 and 8088 b. 32-bit 8086 and 8088 c. 64-bit 8086 and 8088 d. 8-bit 8086 and 8088

Description : Which processor provided 1 MB memory: a. 16-bit 8086 and 8088 b. 32-bit 8086 and 8088 c. 64-bit 8086 and 8088 d. 8-bit 8086 and 8088

Last Answer : a. 16-bit 8086 and 8088

How many bit MC6800 microprocessor: a. 4-bit b. 8-bit c. 16-bit d. 32-bit

Description : How many bit MC6800 microprocessor: a. 4-bit b. 8-bit c. 16-bit d. 32-bit

Last Answer : b. 8-bit

How many bit microprocessor in the era marked beginning of fourth generation: a. 4 bit b. 8 bit c. 16 bit d. 32 bit

Description : How many bit microprocessor in the era marked beginning of fourth generation: a. 4 bit b. 8 bit c. 16 bit d. 32 bit

Last Answer : d. 32 bit

Third generation microprocessor is dominated by____ microprocessor: a. 8 bit b. 4 bit c. 16 bit d. 64 bit

Description : Third generation microprocessor is dominated by____ microprocessor: a. 8 bit b. 4 bit c. 16 bit d. 64 bit

Last Answer : c. 16 bit

The beginning of very efficient____ microprocessor in second generation: a. 4-bit b. 8-bit c. 16-bit d. 64-bit

Description : The beginning of very efficient____ microprocessor in second generation: a. 4-bit b. 8-bit c. 16-bit d. 64-bit

Last Answer : b. 8-bit

A stack is a. an 8-bit register in the microprocessor b. a 16-bit register in the microprocessor c. a set of memory locations in R/WM reserved for storing information temporarily during the execution of computer

Description : A stack is a. an 8-bit register in the microprocessor b. a 16-bit register in the microprocessor c. a set of memory locations in R/WM reserved for storing information temporarily during the execution of computer

Last Answer : c. a set of memory locations in R/WM reserved for storing information temporarily during the execution of computer

For a memory with a 16-bit address space, the addressability is a. 16 bits b. 8 bits c. 2^16 bits d. Cannot be determined

Description : For a memory with a 16-bit address space, the addressability is a. 16 bits b. 8 bits c. 2^16 bits d. Cannot be determined

Last Answer : d. Cannot be determined

How many bit of MAR register: a. 8-bit b. 16-bit c. 32-bit d. 64-bit

Description : How many bit of MAR register: a. 8-bit b. 16-bit c. 32-bit d. 64-bit

Last Answer : b. 16-bit

The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit

Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit

Last Answer : b. 10 bit

Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Last Answer : d) 16, MCS96

Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Last Answer : d) 16, MCS96

The intel 8086 microprocessor is a _______ processor A. 8 bit B. 16 bit C. 32 bit D. 4 bit

Description : The intel 8086 microprocessor is a _______ processor A. 8 bit B. 16 bit C. 32 bit D. 4 bit

Last Answer : The intel 8086 microprocessor is a 16 bit processor 

A collection of 8 bits is called a. byte b. word c. record

Description : A collection of 8 bits is called a. byte b. word c. record

Last Answer : a. byte

The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these

Description : The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these

Last Answer : a. Read

The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B

Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B

Last Answer : b. Write

The upper red arrow show that CPU sends out the control signals____ and _____ indicate the data is read from the memory: a. Memory request b. Read c. Both A and B d. None of these

Description : The upper red arrow show that CPU sends out the control signals____ and _____ indicate the data is read from the memory: a. Memory request b. Read c. Both A and B d. None of these

Last Answer : c. Both A and B

CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these

Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these

Last Answer : b. Data bus

The virtual address generated by a CPU is 32 bits. The Translation Lookaside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4- cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is (A) 12 bits (B) 15 bits (C) 16 bits (D) 20 bits

Description : The virtual address generated by a CPU is 32 bits. The Translation Lookaside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4- cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is (A) 12 bits (B) 15 bits (C) 16 bits (D) 20 bits

Last Answer : (C) 16 bits Explanation: VirtualAddress = 32 bits PageSize = 4KB = 12 bits therefore : VPNTag = 20 bits, OffsetTag = 12 bits TLBEntryLength = VPNTag = 20 bits TotalTLBEntries = 64, 4-way implies ... therefore : TLBIndex = 4 bits TLBTag = TLBEntryLength - TLBIndex = 20 - 4 = 16 bits

List the 16 – bit registers of 8085 microprocessor.

Description : List the 16 – bit registers of 8085 microprocessor.

Last Answer : Stack pointer (SP) and Program counter (PC).

Which is 16 Bit microprocessor: a. 8088 b. 8086 c. 8085 d. All of these

Description : Which is 16 Bit microprocessor: a. 8088 b. 8086 c. 8085 d. All of these

Last Answer : d. All of these

Calculator are based on______ microprocessor: a. 4 bit b. 16 bit c. 32 bit d. 64 bit

Description : Calculator are based on______ microprocessor: a. 4 bit b. 16 bit c. 32 bit d. 64 bit

Last Answer : a. 4 bit