Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : b) address valid strobe select
Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option ... b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : c) EA, high, external, internal
Description : Which of the following statements on DRAM are correct? i) Page mode read operation is faster than RAS read. ii) RAS input remains active during column address strobe. iii) The row and column addresses are strobed into the ... RAS and CAS inputs respectively. a) i & iii b) i & ii c) all d) iii
Last Answer : d) iii
Description : In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller
Last Answer : a) 1, 8bit, single processor
Last Answer : c) 2, 9 bit, multiple processors
Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH
Last Answer : c) 2000 to 3FFFH
Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B
Last Answer : b. Write
Description : 8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, register ... c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register
Last Answer : c) 232 byte, five 8bit, register to register
Description : 8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, ... c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register
Last Answer : d) 232 byte, six 8 bit, register to register
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96
Last Answer : d) 16, MCS96
Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width
Last Answer : c) Address bus width
Description : 8088 microprocessor differs with 8086 microprocessor in a) Data width on the output b) Address capability c) Support of coprocessor d) Support of MAX / MIN mode
Last Answer : a) Data width on the output
Description : Virtual Mode Flag bit can be set using ____ instruction or any task switch operation only in the _____ mode a) IRET, Virtual b) POPF, Real c) IRET, protected d) POPF, protected
Last Answer : b) POPF, Real
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit
Last Answer : b. 10 bit
Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these
Last Answer : c. 65536
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus is 20 bit
Description : In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor communication and is of ____ bit address. a) SM1, 9EH b) TB8 , 9CH c) SM2 , 9DH d) SM0, 9FH
Last Answer : c) SM2 , 9DH
Description : Which is not the control bus signal: a. READ b. WRITE c. RESET
Last Answer : c. RESET
Description : In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C. a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2
Last Answer : a) 3, Mode2
Description : In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the ____. a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte d) LILO byte by byte.
Last Answer : a) FIFO byte by byte
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus
Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus
Last Answer : b. Address bus
Description : 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv
Last Answer : c) 4, i,ii,iii
Description : In 8096 we have _____interrupt sources and _______ interrupt vectors. a) 18, 8 b) 21, 6 c) 21, 8 d) 16, 8
Last Answer : c) 21, 8
Last Answer : c) 21,
Description : How many synchronous and asynchronous modes are there in serial port of 8096? M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/1 Microprocessors and Microcontrollers/ Multiple Choice Questions Architecture of Micro ... 2, 2 respectively b) 3,1 respectively c) 1, 3 respectively d) 1, 2 respectively
Last Answer : c) 1, 3 respectively
Description : The system is notified of a read or write operation by ___________ a) Appending an extra bit of the address b) Enabling the read or write bits of the devices c) Raising an appropriate interrupt signal d) Sending a special signal along the BUS
Last Answer : Sending a special signal along the BUS
Description : VAM stands for: a. Valid memory address b. Virtual memory address c. Variable memory address d. None of these
Last Answer : a. Valid memory address
Description : Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.
Last Answer : a) Because 8085 processor has 8 bit ALU.
Description : The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register
Last Answer : The microprocessor can read/write 16 bit data from or to memory
Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these
Last Answer : a. CPU
Description : __ bit in ICW1 indicates whether the 8259A is cascade mode or not? a) LTIM=0 b) LTIM=1 c) SNGL=0 d) SNGL=1
Last Answer : c) SNGL=0
Description : Which are the READ operation can in simple steps: a. Address b. Data c. Control d. All of these
Description : In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU. a) CS, high b) A0, high c) IRQ, high d) STB, high
Last Answer : c) IRQ, high
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64
Last Answer : b. 32
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately (A) 1 MHz. (B) 500 MHz. (C) 2 MHz. (D) 4 MHz.
Last Answer : Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.
Description : A 3 -stage ripple counter has Flip Flop with propagation delay of 25 nsec and pulse width of strobe input 10 nsec. Then the maximum operating frequency at which counter operates reliably is
Last Answer : A 3 -stage ripple counter has Flip Flop with propagation delay of 25 nsec and pulse width of strobe input 10 nsec. Then the maximum operating frequency at which counter operates reliably is 12.67 MHz