Description : Which statement is valid? a. 1KB = 1024 bytes b. 1 MB=2048 bytes c. 1 MB = 1000 kilobytes d. 1 KB = 1000 bytes
Last Answer : a. 1KB = 1024 bytes
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus is 20 bit
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these
Last Answer : c. 65536
Description : The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,
Last Answer : a) 8 byte, on-chip 128 byte RAM.
Description : How many address lines are needed to address each memory locations in a 2048 x 4 memory chip? a. 10 b. 11 c. 8 d. 12
Last Answer : b. 11
Description : How many address lines are needed to address each memory location in a 2048 x 4 memory chip? a. 10 b. 11 c. 8 d. 12
Description : how many address lines are needed to address each machine location in a 2048 x 4 memory chip? a. 10 b. 11 c. 8 d. 12
Description : Which statement is valid? A) 1KB = 1024 bytes B) 1 MB=2048 bytes C) 1 MB = 1000 kilobytes D) 1 KB = 1000 bytes
Last Answer : Answer : A
Last Answer : 1KB = 1024 bytes
Description : For a memory with a 16-bit address space, the addressability is a. 16 bits b. 8 bits c. 2^16 bits d. Cannot be determined
Last Answer : d. Cannot be determined
Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : c) bus width select
Last Answer : b) address valid strobe select
Description : ROM d) 8 bit, on chip 128 byte RAM. 3. After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H
Last Answer : c) 7H
Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64
Last Answer : b. 32
Description : How many address lines in a 4096 x 8 EPROM CHIP?
Last Answer : 12 address lines.
Description : A stack pointer is a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory. b. a register that decodes and executes 16-bit arithmetic expression. c. The first memory location where a subroutine address is stored. d. a register in which flag bits are stored
Last Answer : a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory.
Description : _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus
Last Answer : d. Bus
Description : Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.
Last Answer : a) Because 8085 processor has 8 bit ALU.
Description : Which statement is wrong according to linear decoding : a. Address map is not contiguous. b. Confects occur if two of the select lines become active at the same time c. If all unused address lines are not used as chip selectors then these unused lines become don’t cares d. None of these
Last Answer : d. None of these
Description : Instructions and memory address are represented by a. Character code b. Binary codes c. Binary word d. Parity bit
Last Answer : b. Binary codes
Description : Which processor provided 1 MB memory: a. 16-bit 8086 and 8088 b. 32-bit 8086 and 8088 c. 64-bit 8086 and 8088 d. 8-bit 8086 and 8088
Last Answer : a. 16-bit 8086 and 8088
Description : How many bit MC6800 microprocessor: a. 4-bit b. 8-bit c. 16-bit d. 32-bit
Last Answer : b. 8-bit
Description : How many bit microprocessor in the era marked beginning of fourth generation: a. 4 bit b. 8 bit c. 16 bit d. 32 bit
Last Answer : d. 32 bit
Description : Third generation microprocessor is dominated by____ microprocessor: a. 8 bit b. 4 bit c. 16 bit d. 64 bit
Last Answer : c. 16 bit
Description : The beginning of very efficient____ microprocessor in second generation: a. 4-bit b. 8-bit c. 16-bit d. 64-bit
Description : A stack is a. an 8-bit register in the microprocessor b. a 16-bit register in the microprocessor c. a set of memory locations in R/WM reserved for storing information temporarily during the execution of computer
Last Answer : c. a set of memory locations in R/WM reserved for storing information temporarily during the execution of computer
Description : How many bit of MAR register: a. 8-bit b. 16-bit c. 32-bit d. 64-bit
Last Answer : b. 16-bit
Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96
Last Answer : d) 16, MCS96
Description : In 8279, the keyboard entries are debounced and stored in an _________, that is further accessed by the CPU to read the key codes. a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO
Last Answer : b) 8-byte FIFO
Description : The intel 8086 microprocessor is a _______ processor A. 8 bit B. 16 bit C. 32 bit D. 4 bit
Last Answer : The intel 8086 microprocessor is a 16 bit processor
Description : In a 16-bit microprocessor, a single word is A) 16 bit data B) 32 bit data C) 8 bit data D) 64 bit data
Last Answer : In a 16-bit microprocessor, a single word is 16 bit data
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Last Answer : b. Address bus
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width
Last Answer : c) Address bus width
Description : A 20-bit address bus allows access to a memory of capacity (1) 1 Mb (2) 2 Mb (3) 32 Mb (4) 64 Mb
Last Answer : 1MB
Description : On a PC, how much memory is available to application software? a. 1024 KB b. 760 KB c. 640 KB d. 560 KB
Last Answer : c. 640 KB
Description : The term gigabyte refers to a. 1024 bytes b. 1024 kilobytes c. 1024 megabytes d. 1024 gigabyte
Last Answer : c. 1024 megabytes
Description : The address of a class B host is to be split into subnets with a 6-bit subnet number. What is the maximum number of subnets and the maximum number of hosts in each subnet? a. 62 subnets and 262142 hosts. b. 64 subnets and 262142 hosts. c. 62 subnets and 1022 hosts. d. 64 subnets and 1024 hosts
Last Answer : c. 62 subnets and 1022 hosts.