A new signal group on the 80486 is the ______.
a) PARITY
b) DP0-DP3 c) PCHK
d) all

1 Answer

Answer :

b) DP0-DP3

Related questions

Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64

Last Answer : b. 32

Description : Which of the following is used for manufacturing chips? a. Control bus b. Control unit c. Parity unit d. Semiconductor

Last Answer : d. Semiconductor

Description : Instructions and memory address are represented by a. Character code b. Binary codes c. Binary word d. Parity bit

Last Answer : b. Binary codes

Description : Which of the following is associated with error detector? a. Odd parity bit b. Even parity bit c. Both of the above d. None of above

Last Answer : c. Both of the above

Description : What is the signal classification of 8085

Last Answer : All the signals of 8085 can be classified into 6 groups • Address bus • Data bus • Control and status signals • Power supply and frequency signals • Externally initiated signals • Serial I/O ports

Description : What is the function of IO/M signal in the 8085?

Last Answer : It is a status signal. It is used to differentiate between memory locations and I/O operations. When this signal is low (IO/M = 0) it denotes the memory related operations. When this signal is high (IO/M = 1) it denotes an I/O operation.

Description : A technique used by codes to convert an analog signal into a digital bit stream is known as a. Pulse code modulation b. Pulse stretcher c. Query processing d. Queue management

Last Answer : a. Pulse code modulation

Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these

Last Answer : a. DMA acknowledge signal

Description : The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these

Last Answer : a. Read

Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B

Last Answer : b. Write

Description : Which statement is false about WR signal: a. WR signal controls the input buffer b. The bar over WR means that this is an active low signal c. The bar over WR means that this is an active high signal d. If WR is 0 then the input data reaches the latch input

Last Answer : c. The bar over WR means that this is an active high signal

Description : Which is not the control bus signal: a. READ b. WRITE c. RESET

Last Answer : c. RESET

Description : Which pin of port 3 is has an alternative function as write control signal for external data memory? a) P3.8 b) P3.3 c) P3.6 d) P3.1

Last Answer : d) P3.1

Description : Which pin of port 3 is has an alternative function as write control signal for external data memory? a) P3.8 b) P3.3 c) P3.6 d) P3.1

Last Answer : c) P3.6

Description : BHE of 8086 microprocessor signal is used to interface the a) Even bank memory b) Odd bank memory c) I/O d) DMA

Last Answer : b) Odd bank memory

Description : L2 cache memory is places at ______ a. On Processor b. On Mother Board c. On Memory d. All of these

Last Answer : b. On Mother Board

Description : L1 cache memory is places at ______ a. On Processor b. On Mother Board c. On Memory d. All of these

Last Answer : a. On Processor

Description : For the number A[15:0] = 0110110010001111, A[14:13] is ______ A[3:2]. a. less than b. greater than c. the same as d . cannot be determined

Last Answer : c. the same as

Description : When the write enable input is not asserted, the gated D latch ______ its output. a. can not change b. clears c. sets d. complements

Last Answer : a. can not change

Description : The external device is connected to a pin called the ______ pin on the processor chip. a. Interrupt b. Transfer c. Both d. None of these

Last Answer : a. Interrupt

Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these

Last Answer : a. Fully decoding

Description : The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann

Last Answer : d. Von Neumann

Description : The interrupt vector table of 80386 has been allocated ______ space starting from _______ to _______. a) 1Kbyte, 00000H, 003FFH b) 2Kbyte, 10000H, 004FFH c) 3Kbyte, 01000H, 007FFH d) 4Kbyte, 01000H, 009FFH

Last Answer : c) 3Kbyte, 01000H, 007FFH

Description : ACALL instruction allows specifying ______address in the instruction and calling subroutine within ______ program memory block. a) 2byte, 3K b) 11bit, 2K c) 9bit, 2K d) 1byte, 3K

Last Answer : c) 9bit, 2K

Description : 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv

Last Answer : c) 4, i,ii,iii

Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Last Answer : d) 16, MCS96

Description : The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,

Last Answer : a) 8 byte, on-chip 128 byte RAM.

Description : The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit

Last Answer : c) 40, 8 bit

Description : If ______ and ________ connections are made so that an error condition in 8087 can interrupt to the processor. a) BHE, RQ/GT1 b) BUSY, TEST c) INT, NMI d) RQ/GT0, RQ/GT1

Last Answer : c) INT, NMI

Description : ______ input is available, so that another coprocessor can be connected and function in _________ with the 8087. . a) RQ/GT0, parallel b) RQ/GT1, parallel c) QS1 & QS0, parallel d) S0 & S1, parallel.

Last Answer : a) RQ/GT0, parallel

Description : The coprocessors operate in ______ with a processor on the same buses and with the same instruction _______. a) Parallel, byte stream. b) Series, byte stream. c) Series, bite stream d) Parallel, bite stream.

Last Answer : a) Parallel, byte stream.

Description : 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv

Last Answer : c) 4, i,ii,iii

Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Last Answer : d) 16, MCS96

Description : The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit d) 40, 8 byte

Last Answer : c) 40, 8 bit

Description : RIM is used to check whether, ______ a) The write operation is done or not b) The interrupt is Masked or not c) a & b

Last Answer : b) The interrupt is Masked or not

Description : The purpose of the microprocessor is to control ______  A. memory B. switches C. processing D. tasks

Last Answer : The purpose of the microprocessor is to control memory 

Description : Microprocessor is the ______ of the computer and it perform all the computational tasks  A. main B. heart C. important D. simple

Last Answer : Microprocessor is the heart of the computer and it performs all the computational tasks

Description : List out the five categories of the 8085 instructions. Give examples of the instructions for each group.

Last Answer : • Data transfer group – MOV, MVI, LXI. • Arithmetic group – ADD, SUB, INR. • Logical group –ANA, XRA, CMP. • Branch group – JMP, JNZ, CALL. • Stack I/O and Machine control group – PUSH, POP, IN, HLT.

Description : How many group of memory unit: a. Four b. Three c. Two d. One

Last Answer : b. Three

Description : A group of magnetic tapes, videos or terminals usually under the control of one master is a. Cylinder b. Surface c. Track d. Cluster

Last Answer : d. Cluster

Description : What is the name of the new color laptop computer which is powered by a 386 processor at 33 MHz and is built by Epson? a. AX3/33 b. NEC-20 c. Magnum 2000 d. HCL-3000

Last Answer : a. AX3/33

Description : ____is used to control the cache with two new control bits not present in the 80386 microprocessor. What are the bits used to control the 8K byte cache? a) CR0, CD, NW b) CR0, NW, PWT c) Control Register Zero, PWT, PCD d) none

Last Answer : d) none

Description : Is this an indication that women have finally reached parity with men in politics?

Last Answer : No, it just means that the type of woman attracted by politics is the same as the type of man.

Description : Will parity for mental health payments make mental illness better understood and accepted?

Last Answer : A new law changing people's opinions unrealistic. For example, hate crime laws are in place. Has hate crime ceased? No. The equality with physical injuries will probably make skeptics ... ] issue? Only when individuals change their own individual opinions by choice will the situation improve.

Description : What is purchasing power parity -SST 10th

Last Answer : This answer was deleted by our moderators...

Description : What is set parity ?

Last Answer : If two or more sets of elements are the same , they are called set equivalents.

Description : Which of the following is associated with error detector? A) Odd parity bit B) Even parity bit C) Both of the above D) None of above

Last Answer : Answer : C

Description : Which of the following is used for manufacturing chips? A) Control bus B) Control unit C) Parity unit D) Semiconductor

Last Answer : Answer : D

Description : Instructions and memory address are represented by A) Character code B) Binary codes C) Binary word D) Parity bit

Last Answer : Answer : B

Description : Which flag indicates the number of 1 bit that results from an operation? a) Zero b) Parity c) Auxiliary d) Carry

Last Answer : Answer: b Explanation: The parity flag indicates the number of 1 bits in any operation. The resultant bit is called the parity bit. The main aim of the parity bit is to check for errors