Description : The external device is connected to a pin called the ______ pin on the processor chip. a. Interrupt b. Transfer c. Both d. None of these
Last Answer : a. Interrupt
Description : The interrupt vector table of 80386 has been allocated ______ space starting from _______ to _______. a) 1Kbyte, 00000H, 003FFH b) 2Kbyte, 10000H, 004FFH c) 3Kbyte, 01000H, 007FFH d) 4Kbyte, 01000H, 009FFH
Last Answer : c) 3Kbyte, 01000H, 007FFH
Description : If ______ and ________ connections are made so that an error condition in 8087 can interrupt to the processor. a) BHE, RQ/GT1 b) BUSY, TEST c) INT, NMI d) RQ/GT0, RQ/GT1
Last Answer : c) INT, NMI
Description : Which interrupt is not level sensitive in 8085? a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-trigging interrupt. c) a & b.
Last Answer : b) RST7.5 is a raising edge-trigging interrupt.
Description : What is meant by interrupt?
Last Answer : Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine.
Description : List the four instructions which control the interrupt structure of the 8085 microprocessor.
Last Answer : • DI ( Disable Interrupts ) • EI ( Enable Interrupts ) • RIM ( Read Interrupt Masks ) • SIM ( Set Interrupt Masks )
Description : Serial port interrupt is generated, if ____ bits are seta) IE b) RI, IE c) IP, TI d) RI, TI
Last Answer : d) RI, TI
Description : Which are the flags of status register: a. Over flow flag b. Carry flag c. Half carry flag d. Zero flag e. Interrupt flag f. Negative flag g. All of these
Last Answer : g. All of these
Description : Serial port vector address is of _______. And causes an interrupt when ________. a) 0013H, either TI or RI flag is set b) 0023H, either TI or RI flag is reset c) 0013H, either TI or RI flag is reset d) 0023H, either TI or RI flag is set
Last Answer : a) 0013H, either TI or RI flag is set
Description : In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____. a) 000BH, a high to low transition on pin INT1 b) 001BH, a low to high transition on pin INT1 c) 0013H, a high to low transition on pin INT1 d) 0023H, a low to high transition on pin INT1
Last Answer : a) 000BH, a high to low transition on pin INT1
Description : In 8096 we have _____interrupt sources and _______ interrupt vectors. a) 18, 8 b) 21, 6 c) 21, 8 d) 16, 8
Last Answer : c) 21, 8
Description : In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1
Last Answer : a)IE1
Description : Serial port interrupt is generated, if ____ bits are set a) IE b) RI, IE c) IP, TI d) RI, TI
Last Answer : a) IE
Description : 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s are in master slave configuration the number of interrupts available to the 8086 microprocessor is a) 8 b) 16 c) 15 d) 64
Last Answer : a) 8
Description : In 8279, a scanned sensor matrix mode, if a sensor changes its state, the ___ line goes ____ to interrupt the CPU. a) CS, high b) A0, high c) IRQ, high d) STB, high
Last Answer : c) IRQ, high
Last Answer : c) 21,
Last Answer : c)IE0
Description : What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that can be turned off by the programmer. c) none
Last Answer : b) An interrupt that can be turned off by the programmer.
Description : What is SIM? a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
Last Answer : c) Set Interrupt Mask.
Description : Which interrupt has the highest priority? a) INTR b) TRAP c) RST6.5
Last Answer : c) RST6.5
Description : Which of the following statements on DRAM are correct? i) Page mode read operation is faster than RAS read. ii) RAS input remains active during column address strobe. iii) The row and column addresses are strobed into the ... RAS and CAS inputs respectively. a) i & iii b) i & ii c) all d) iii
Last Answer : d) iii
Description : A microporgram is sequencer perform the operation a. read b. write c. execute d. read and write e. read and execute
Last Answer : e. read and execute
Description : The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these
Last Answer : a. Read
Description : The system is notified of a read or write operation by ___________ a) Appending an extra bit of the address b) Enabling the read or write bits of the devices c) Raising an appropriate interrupt signal d) Sending a special signal along the BUS
Last Answer : Sending a special signal along the BUS
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : ______ input is available, so that another coprocessor can be connected and function in _________ with the 8087. . a) RQ/GT0, parallel b) RQ/GT1, parallel c) QS1 & QS0, parallel d) S0 & S1, parallel.
Last Answer : a) RQ/GT0, parallel
Description : When the write enable input is not asserted, the gated D latch ______ its output. a. can not change b. clears c. sets d. complements
Last Answer : a. can not change
Description : Processors of all computers, whether micro, mini or mainframe must have a. ALU b. Primary Storage c. Control unit d. All of above
Last Answer : b. Primary Storage
Description : A memory that is capable of determining whether a given datum is contained in one of its address is a. ROM b. PROM c. CAM d. RAM
Last Answer : c. CAM
Description : The ___ bit decides whether it is a system descriptor or code/data segment descriptor a) P b) S c) D d) G
Last Answer : a) P
Description : __ bit in ICW1 indicates whether the 8259A is cascade mode or not? a) LTIM=0 b) LTIM=1 c) SNGL=0 d) SNGL=1
Last Answer : c) SNGL=0
Description : A job has four pages A, B, C, D and the main memory has two page frames only. The job needs to process its pages in following order: ABACABDBACD Assuming that a page interrupt occurs when a new page is brought in the main ... replacement algorithms are (A) 9 and 7 (B) 7 and 6 (C) 9 and 8 (D) 8 and 6
Last Answer : (C) 9 and 8
Description : Control signals used for DMA operation are ____________
Last Answer : HOLD & HLDA.
Description : Who is the represents the fundamental process in the operation of the CPU: a. The fetch-execute cycle and pipelining b. The assembly c. Both A and B d. None of these
Last Answer : a. The fetch-execute cycle and pipelining
Description : CPU does not perform the operation a. data transfer b. logic operation c. arithmetic operation d. all of above
Last Answer : b. logic operation
Description : The necessary steps carried out to perform the operation of accessing either memory or I/O Device, constitute a ___________________ a) fetch operation b) execute operation c) machine cycle
Last Answer : c) machine cycle
Description : The use of spooler programs and/or …. Hardware allows personal computer operators to do the processing work at the same time a printing operation is in progress a. Registered mails b. Memory c. CPU d. Buffer
Last Answer : d. Buffer
Description : The secondary storage devices can only store data but they cannot perform a. Arithmetic Operation b. Logic operation c. Fetch operations d. Either of the above
Last Answer : d. Either of the above
Description : Which operation is not performed by computer a. Inputting b. Processing c. Controlling d. Understanding
Last Answer : d. Understanding
Description : A___ on this pin indicates a memory operation: a. Low b. High c. Medium d. None of these
Last Answer : a. Low
Description : Which are the READ operation can in simple steps: a. Address b. Data c. Control d. All of these
Last Answer : d. All of these
Description : MOC stands for: a. Memory operation complex b. Micro operation complex c. Memory operation complete d. None of these
Last Answer : c. Memory operation complete
Description : Which is the basic stack operation: a. PUSH b. POP c. BOTH A and B d. None of these
Last Answer : c. BOTH A and B
Description : Single address computer instruction has two parts: a. The operation code b. The operand c. A and B d. None of these
Last Answer : c. A and B
Description : To prevent another master from taking over the bus during a critical operation, the 486 can assert its _____signal. a) LOCK# or PLOCK# b) HOLD or BOFF c) HLDA d) HOLD
Last Answer : a) LOCK# or PLOCK#
Description : Virtual Mode Flag bit can be set using ____ instruction or any task switch operation only in the _____ mode a) IRET, Virtual b) POPF, Real c) IRET, protected d) POPF, protected
Last Answer : b) POPF, Real
Description : In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C. a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2
Last Answer : a) 3, Mode2
Description : In 8086 microprocessor one of the following instructions is executed before an arithmetic operation a) AAM b) AAD c) DAS d) DAA
Last Answer : b) AAD
Description : In 8086 the overflow flag is set when a) The sum is more than 16 bits b) Signed numbers go out of their range after an arithmetic operation c) Carry and sign flags are set
Last Answer : b) Signed numbers go out of their range after an arithmetic operation