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Answer :

The conversion time of a 12 bit successive approximation A/D converter using a 1 MHz clock is 12μs.

Related questions

Last Answer : A 12 bit counter type A/D converter uses a 1 MHz clock. Its maximum conversion time is 4096μs.

Last Answer : For a certain 4 bit successive approximation A/D converter, the maximum ladder output is +8V. if a constant +6V is applied to the analog input the sequence of binary states for the SA register is 0110.

Last Answer : A 12 bit counter type A/D converter uses a 1 MHz clock. If the full scale output is +10V, its resolution output is 2.44mV.

Description : The A/D converter whose conversion time is independent of the number of bits is (A) Dual slope (B) Counter type (C) Parallel conversion (D) Successive approximation.

Last Answer : Ans: C The A/D converter whose conversion time is independent of the Number of bits is Parallel conversion. (This type uses an array of comparators connected in parallel and comparators compare the input voltage at a particular ratio of the reference voltage).

Description : The speed of conversion is maximum in (A) Successive-approximation A/D converter. (B) Parallel-comparative A/D converter. (C) Counter ramp A/D converter. (D) Dual-slope A/D converter.

Last Answer : Ans: B The speed of conversion is maximum in Parallel-comparator A/D converter (Speed of conversion is maximum because the comparisons of the input voltage are carried out simultaneously.)

Description : The conversation speed of an analog to digital converter is maximum with the following technique. (A) Dual slope AD converter. (B) Serial comparator AD converter. (C) Successive approximation AD converter. (D) Parallel comparator AD converter.

Last Answer : (D) Parallel comparator AD converter.

Description : In successive-approximation A/D converter, offset voltage equal to 1/2 LSB is added to the D/A converter's output. This is done to (A) Improve the speed of operation. (B) Reduce the maximum ... Increase the number of bits at the output. (D) Increase the range of input voltage that can be converted

Last Answer : (B) Reduce the maximum quantization error.

Description : In successive approximation converter input to the comparator is through (A) DAC (B) Latch (C) Flip-flop (D) Sample and hold circuit

Last Answer : In successive approximation converter input to the comparator is through DAC 

Last Answer : An 8 bit converter type A/D converter makes at least 8000conversions/sec. The clock frequency used is 2MHz.

Last Answer : The resolution of a 12 bit D/A converter using a binary ladder is 0.02%.

Description : Consider a 32 - bit microprocessor, with a 16 - bit external data bus, driven by an 8 MHz input clock. Assume that the microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What ... (A) 8x106 bytes/sec (B) 4x106 bytes/sec (C) 16x106 bytes/sec (D) 4x109 bytes/sec 

Last Answer : (B) 4x106 bytes/sec

Description : Where can I find the detailed information about Successive Approximation method and discrete newton method??

Last Answer : answer:A DISCRETE NEWTON ALGORITHM FOR MINIMIZING A FUNCTION OF MANY VARIABLES SUCCESSIVE APPROXIMATIONS

Description : Where are the successive approximation type ADC’s used?

Last Answer : The Successive approximation ADCs are used in applications such as data loggers & instrumentation where conversion speed is important.

Description : Explain in brief the principle of operation of successive Approximation ADC.

Last Answer : The circuit of successive approximation ADC consists of a successive approximation register (SAR), to find the required value of each bit by trial & error.With the arrival of START command, SAR sets the MSB ... /P signal. This O/P is low or High. This process continues until all bits are checked.

Description : Draw block diagram of successive approximation digital voltmeter. State its two advantages and two disadvantages

Last Answer : Block diagram Or Advantages: o It is economical method of analog to digital conversion. o The resolution is up to 5 important digits are obtained. Disadvantages: o ... depends on which type of switches are used. o The conversion time required for digital to analog converter.

Description : Successive approximation technique is used for

Last Answer : Successive approximation technique is used for A to D Conversion

Description : What is the common up-converter and down-converter IF? A. 36 MHz B. 40 MHz C. 70 MHz D. 500 MHz

Last Answer : C. 70 MHz

Description : What is the common up-converter and down-converter IF for microwave communications? A. 60 MHz B. 80 MHz C. 120 MHz D. 70 MHz

Last Answer : D. 70 MHz

Description : The catalytic converter for conversion of SO2 to SO3 by contact process should have a feed with SO2 content between (A) 2-5 % (B) 7-10 % (C) 12-15 % (D) 20-25 %

Last Answer : (B) 7-10 %

Description : The maximum clock frequency is _ a. 45 MHZ b. 50 MHZ c. 52 MHZ d. 68 MHZ

Last Answer : b. 50 MHZ

Description : In 8085 microprocessor, the digit 5 indicates that the microprocessor needs (1) -5 volts, +5 volts supply (2) +5 volts supply only (3) -5 volts supply only (4) 5 MHz clock

Last Answer : Answer: 2

Description : The clock frequency of an 8085 microprocessor based system is 3 MHz. What should be the minimum pulse width of the INTR signal so that it is recognized successfully? A) 5.6 µs B) 5.7 µs C) 5.8 µs D) 5.9 µs

Last Answer : The clock frequency of an 8085 microprocessor based system is 3 MHz. What should be the minimum pulse width of the INTR signal so that it is recognized successfully? A) 5.6 µs B) 5.7 µs C) 5.8 µs D) 5.9 µs

Description : Classification of protocol that interprets a frame of data as a group of successive bit combined into predetermined pattern of fixed length, usually 8 bits each.

Last Answer : Character and Byte-oriented protocols

Description : The code where all successive numbers differ from their preceding number by single bit is (A) Binary code. (B) BCD. (C) Excess – 3. (D) Gray.

Last Answer : Ans: D The code where all successive numbers differ from their preceding number by single bit is Gray Code. (It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next.)

Description : Julie is going on an extended trip for three weeks. She lives in a remote area where there are frequent electrical power outages which can last up to three or four days. Julie has quite a bit of food ... power, while another house may have no power. She won?t be able to have a neighbor chec -Riddles

Last Answer : One thing Julie could do is freeze a tray of ice-cubes, and turn the tray of ice upside down in her freezer. When she comes home, she should check the tray. If the ice cubes are still in the ... clean out the freezer. She will have to make a judgment call if the ice-cubes are only slightly thawed.

Description : A device that connects two dissimilar networks and performs the protocol conversion. A. Gateway B. Coupler C. Transformer D. Converter

Last Answer : A. Gateway

Description : Fauser Montecatini converter is used for (A) Ammonia synthesis (e.g. at FCI Sindri, India) (B) Methanation of CO and CO2 (C) Shift conversion (i.e. CO to CO2 ) (D) None of these

Last Answer : (A) Ammonia synthesis (e.g. at FCI Sindri, India)

Description : Automobile exhaust is passed through two compartments catalytic converter employing platinum as catalyst for (A) Conversion of CO into CO2 in the second compartment (B) Conversion of NOx into N2 and NH3 in the first ... of unburnt hydrocarbon fuel in the second compartment (D) All (A), (B) and (C)

Last Answer : (D) All (A), (B) and (C)

Description : In the converter of the contact process for the manufacture of H2SO4 the equilibrium conversion of SO2__________ (i) __________ with increase in temperature and __________ (ii) __________ with increase in the mole ratio ... increases (C) (i) increases (ii) increases (D) (i) decreases (ii) decreases

Last Answer : (B) (i) decreases (ii) increases

Description : Conversion of SO2 to SO3 in Monsanto 4-pass converter is about __________ percent. (A) 80 (B) 90 (C) 98 (D) 100

Last Answer : (C) 98

Description : In multistage equilibrium conversion of SO2 to SO3 (2SO2 + O2 ⇌ 2SO3 ), the reverse reaction becomes appreciable at a temperature of 550° C. The percentage equilibrium conversion of SO2 to ... some quantity of SO3 during intermediate stage (D) Maintaining low temperature & pressure in the converter

Last Answer : (C) Removing some quantity of SO3 during intermediate stage

Description : Pick out the wrong statement. (A) Conversion of SO2 to SO3 in Monsanto-4 pass converter is about 98% (B) The chemical formula of oleum is H2S2O7 , which is formed by saturating ... but technical sulphuric acid (D) Decomposition of sulphuric acid on heating does not start before its boiling

Last Answer : (D) Decomposition of sulphuric acid on heating does not start before its boiling

Description : Multistage catalytic converter is not used in the (A) Conversion of SO2 to SO3 (B) NH3 synthesis reaction (C) Both (A) and (B) (D) Neither (A) nor (B)

Last Answer : (B) NH3 synthesis reaction

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Last Answer : (B) 80

Description : Consider the following transportation problem: The initial basic feasible solution of the above transportation problem using Vogel's Approximation Method(VAM) is given below: The solution of the ... degenerate solution (B) is optimum solution (C) needs to improve (D) is infeasible solution

Last Answer : (B) is optimum solution

Description : Consider the following transportation problem :  The transportation cost in the initial basic feasible solution of the above transportation problem using Vogel’s Approximation method is : (A) 1450 (B) 1465 (C) 1480 (D) 1520

Last Answer : (B) 1465

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Last Answer : (D) I, II and III only

Description : The number of comparators required in a 3-bit comparator type analog to digital converter is  A) 2 B) 3 C) 7 D) 8 

Last Answer : Number of comparators =2^n -1= 2^3 -1=7

Description : In a weighted-resistor digital-to-analog converter with 8-bit input, if the resistance corresponding to the MSB is 2K, what will be the resistance corresponding to the LSB?  (a) 250 Ω (d) 512 KΩ (c) 256 KΩ (d) 25.5 Ω

Last Answer : In a weighted-resistor digital-to-analog converter with 8-bit input, if the resistance corresponding to the MSB is 2K, what will be the resistance corresponding to the LSB?  (a) 250 Ω (d) 512 KΩ (c) 256 KΩ (d) 25.5 Ω

Description : The percent resolution of an 8 -bit D/A converter is

Last Answer : The percent resolution of an 8 -bit D/A converter is 0.392

Description : A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the analog output for the input code 1010:  (1) 0.3125 V (2) 3.125 V (3) 0.78125 V (4) –3.125 V

Last Answer : 3.125V

Description : Integrating principle in the digital measurement is the conversion of   (a) Voltage to time (b) Voltage to frequency (c) Voltage to current (d) Current to voltage

Last Answer : Integrating principle in the digital measurement is the conversion of Voltage to frequency

Description : A 10 bit resistive divider is constructed such that the current through the LSB resistor is 100μA. The maximum current that will flow through the MSB resistor is 

Last Answer : A 10 bit resistive divider is constructed such that the current through the LSB resistor is 100μA. The maximum current that will flow through the MSB resistor is 51.2mA.

Description : What synchronization is provided so that the start and end of message is identified? A. Carrier B. Character C. Bit D. Clock

Last Answer : B. Character

Description : Asynchronous protocol is A. message oriented B. clock oriented C. bit oriented D. character oriented

Last Answer : D. character oriented

Description : How many clock pulses are required to output a 4-bit number in serial form?

Last Answer : Four.

Description : Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 n sec. The maximum clock frequency is (a) 2.65 MHz (b) 6.25 MHz (c) 5.26 MHz (d) 6.52 MHz 

Last Answer : Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 ns. The maximum clock frequency is 6.25MHz. nff  * Tdelay = 4*40 =160ns so, max. frequency = 1/ (200*10-9 ) = 6.25MHz          

Description : What is the required quality factor for an SSB filter with the following data: center frequency= 1 MHz, the desired attenuation level of the unwanted sideband= 80 dB and the separation between sidebands= 200 Hz? A. 1,250 B. 12,500 C. 125,000 D. 25,000

Last Answer : C. 125,000

Description : Which one of the following statements best defines an estimate? a. An approximation of project time and cost targets, refined throughout the project life cycle. b. A prediction of a future ... . A situation that affects or influences the outcome of the project expressed in time or cost terms

Last Answer : a. An approximation of project time and cost targets, refined throughout the project life cycle.

Description : Which one of the following statements best defines an estimate?  a. An approximation of project time and cost targets, refined throughout the project life  cycle.  b. A prediction of a future ... . A situation that affects or influences the outcome of the project expressed in time or cost terms.

Last Answer : a. An approximation of project time and cost targets, refined throughout the project life  cycle.