Description : State the functions of following pins of 8085 1) SOD 2) HLDA
Last Answer : 1) SOD: Serial Output data SOD pin is used to transmit data serially from accumulator to the external devices connected to the pin. 2) HLDA: Microprocessor generates HLDA signal to acknowledge requesting device after HOLD signal.
Description : What type of control pins are needed in a microprocessor to regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time? a. Bus control b. Interrupts c. Bus arbitration d. Status
Last Answer : c. Bus arbitration
Description : If ______input pin of 80386 if activated, allows address pipelining during 80386 bus cycles. a) BS16 b) NA c) PEREQ d) ADS
Last Answer : a) BS16
Description : The marry boff kill game...?
Last Answer : marry Ygritte boff Cersei kill Joffrey
Description : Which is used to store critical pieces of data during subroutines and interrupts: a. Stack b. Queue c. Accumulator d. Data register
Last Answer : a. Stack
Description : A group of magnetic tapes, videos or terminals usually under the control of one master is a. Cylinder b. Surface c. Track d. Cluster
Last Answer : d. Cluster
Description : 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s are in master slave configuration the number of interrupts available to the 8086 microprocessor is a) 8 b) 16 c) 15 d) 64
Last Answer : a) 8
Description : Which of the following statements on DRAM are correct? i) Page mode read operation is faster than RAS read. ii) RAS input remains active during column address strobe. iii) The row and column addresses are strobed into the ... RAS and CAS inputs respectively. a) i & iii b) i & ii c) all d) iii
Last Answer : d) iii
Description : System Bus Contains: a. Address Bus b. Data Bus c. Control Bus d. All of these
Last Answer : d. All of these
Description : Which is the components of computer: a. System Bus b. CPU c. Memory Unit d. All of these
Description : The ________ ensures that only one IC is active at a time to avoid a bus conflict caused by two ICs writing different data to the same bus.A.control busB.control instructionsC. address decoder D.CPU
Last Answer : C. address decoder
Description : A 32-bit address bus allows access to a memory of capacity(a) 64 Mb (b) 16 Mb (c) 1Gb (d) 4 Gb 2.Which processor structure is pipelined? a) all x80 processors b) all x85 processors c) all x86 processors
Last Answer : c) all x86 processors
Description : A physical connection between the microprocessor memory and other parts of the m9crocomputer is known as a. Path b. Address bus c. Route d. All of the above
Last Answer : b. Address bus
Description : Which of the following is used for manufacturing chips? a. Control bus b. Control unit c. Parity unit d. Semiconductor
Last Answer : d. Semiconductor
Description : Which is used for manufacturing chips? a. Bus b. Control unit c. Semiconductors d. A and b only
Last Answer : c. Semiconductors
Description : Dot-matrix is a type of a. Tape e. Printer f. Disk g. Bus
Last Answer : e. Printer
Description : Which of the following are the two main components of the CPU? a. Control unit and registers b. Registers and main memory c. Control Unit and ALU d. ALU and bus
Last Answer : c. Control Unit and ALU
Description : The CPU completes yields control of the bus to the DMA controller via: a. DMA acknowledge signal b. DMA integrated signal c. DMA implicitly signal d. None of these
Last Answer : a. DMA acknowledge signal
Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these
Last Answer : a. CPU
Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B
Last Answer : b. Write
Description : The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Address bus b. System bus c. Control bus d. Data bus
Last Answer : a. Address bus
Description : The information on the data bus is transferred to the ______register: a. MOC b. MDR c. VAM d. CPU
Last Answer : b. MDR
Description : Which register is connected to the memory by way of the address bus: a. MAR b. MDR c. SAM d. None of these
Last Answer : a. MAR
Description : Which bus plays a crucial role in I/O: a. System bus b. Control bus c. Address bus d. Both A and B
Last Answer : b. Control bus
Description : The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Fully decoding b. Half decoding c. Both a & b d. None of these
Last Answer : a. Fully decoding
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. 8 bit b. 10 bit c. 12 bit d. 16 bit
Last Answer : b. 10 bit
Description : Which is not the control bus signal: a. READ b. WRITE c. RESET
Last Answer : c. RESET
Description : Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : a. Control bus
Description : CPU can read & write data by using : a. Control bus b. Data bus c. Address bus d. None of these
Last Answer : b. Data bus
Description : The processor 80386/80486 and the Pentium processor uses _____ bits address bus: a. 16 b. 32 c. 36 d. 64
Last Answer : b. 32
Description : A 16 bit address bus can generate___ addresses: a. 32767 b. 25652 c. 65536 d. none of these
Last Answer : c. 65536
Description : Which bus carry addresses: a. System bus b. Address bus c. Control bus d. Data bus
Description : Which Bus connects CPU & level 2 cache: a. Rear side bus b. Front side bus c. Memory side bus d. None of these
Last Answer : b. Front side bus
Description : The network of wires or electronic path ways on mother board back side: a. PCB b. BUS c. BOTH A and B d. None of these
Last Answer : c. BOTH A and B
Description : The external system bus architecture is created using from ______ architecture: a. Pascal b. Dennis Ritchie c. Charles Babbage d. Von Neumann
Last Answer : d. Von Neumann
Description : Which is called superhighway: a. Processor b. Multiplexer c. Backbone bus d. None of these
Last Answer : c. Backbone bus
Description : _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Chip b. Register c. Processor d. Bus
Last Answer : d. Bus
Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : c) bus width select
Last Answer : b) address valid strobe select
Description : What does microprocessor speed depends on? a) Clock b) Data bus width c) Address bus width
Last Answer : c) Address bus width
Description : Why 8085 processor is called an 8 bit processor? a) Because 8085 processor has 8 bit ALU. b) Because 8085 processor has 8 bit data bus. c) a & b.
Last Answer : a) Because 8085 processor has 8 bit ALU.
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus is 20 bit
Description : What is 1.486 rounded to the nearest hundredths?
Last Answer : 1.49
Description : What is 486 dividid by 9?
Last Answer : The quotient is exactly 54
Description : The least number, which when divided by 12, 15, 20 and 54 leaves in each case a remainder of 8 is: A.534 B.486 C.544 D.548 E.None of these
Last Answer : Answer – D (548) Explanation – Required number = (L.C.M. of 12, 15, 20, 54) + 8 = 540 + 8 = 548.
Description : The batting average of runs of a cricket player of 30 innings was 96. How many runs must he make in his next innings so as to increase his average of runs by 12? A) 468 b) 668 C) 648 D) 486
Last Answer : A Given that the total average runs of a cricket player (30 innings) = 96 After 31 innings = 108 Required number of runs = (108 * 31 – (96 *30) =3348 – 2880 =468
Description : Which is an integral part of any microcomputer system and its primary purpose is to hold program and data: a. Memory unit b. Register unit c. A and B d. None of these
Last Answer : a. Memory unit
Description : Explain the signals HOLD, READY and SID
Last Answer : HOLD indicates that a peripheral such as DMA controller is requesting the use of address bus, data bus and control bus. READY is used to delay the microprocessor ... slow responding peripheral is ready to send or accept data. SID is used to accept serial data bit by bit
Description : To put the 8085 microprocessor in the wait state(i) lower the-HOLD input (ii) lower the READY input (iii) raise the HOLD input(iv) raise the READY input
Last Answer : (ii) lower the READY input