Description : The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,
Last Answer : a) 8 byte, on-chip 128 byte RAM.
Description : ROM d) 8 bit, on chip 128 byte RAM. 3. After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H
Last Answer : c) 7H
Description : In 8051,After reset the SP register is initialized to address________. a. 8H b) 9H c) 7H
Description : The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit
Last Answer : c) 40, 8 bit
Description : The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit d) 40, 8 byte
Description : After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H
Description : The original ASCII code used…bits of each byte, reserving that last bit for error checking a. 5 b. 6 c. 7 d. 8
Last Answer : c. 7
Description : A 32 bit microprocessor has the word length equal to a. 2 byte b. 32 byte c. 4 byte d. 8 byte
Last Answer : c. 4 byte
Description : 8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, register ... c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register
Last Answer : c) 232 byte, five 8bit, register to register
Description : In 8279, the keyboard entries are debounced and stored in an _________, that is further accessed by the CPU to read the key codes. a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO
Last Answer : b) 8-byte FIFO
Description : 8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, ... c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register
Last Answer : d) 232 byte, six 8 bit, register to register
Description : In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller
Last Answer : a) 1, 8bit, single processor
Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96
Last Answer : d) 16, MCS96
Last Answer : c) 2, 9 bit, multiple processors
Description : A byte consists of a. One bit b. Four bits c. Eight bits d. Sixteen bits
Last Answer : c. Eight bits
Description : The 16 bit register is separated into groups of 4 bit where each groups is called: a. BCD b. Nibble c. Half byte d. None of these
Last Answer : b. Nibble
Description : Which of the following is of bit operations? i) SP ii) P2 iii) TMOD iv) SBUF v) IP a) ii, v only b) ii, iv, v only c) i, v only d) iii, ii only
Last Answer : c) i, v only
Last Answer : a) ii, v only
Description : The ___ bit decides whether it is a system descriptor or code/data segment descriptor a) P b) S c) D d) G
Last Answer : a) P
Description : In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____. a) 000BH, a high to low transition on pin INT1 b) 001BH, a low to high transition on pin INT1 c) 0013H, a high to low transition on pin INT1 d) 0023H, a low to high transition on pin INT1
Last Answer : a) 000BH, a high to low transition on pin INT1
Description : In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1
Last Answer : a)IE1
Last Answer : c)IE0
Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB
Last Answer : b. 6KB
Description : In 8086 microprocessor , the address bus is ________ bit wide A. 12 bit B. 10 bit C. 16 bit D. 20 bit
Last Answer : In 8086 microprocessor, the address bus is 20 bit
Description : A collection of 8 bits is called a. byte b. word c. record
Last Answer : a. byte
Description : The value memvar must be transferred to the ___: a. Computer b. CPU c. Both A and B d. None of these
Last Answer : b. CPU
Description : Steps involved to fetch a byte in 8085
Last Answer : i. The PC places the 16-bit memory address on the address bus ii. The control unit sends the control signal RD to enable the memory chip iii. The byte from ... byte is placed in the instruction decoder of the microprocessor and the task is carried out according to the instruction
Description : Because we wish to allow each ASCII code to occupy one location in memory, most memories are _____ addressable. a. BYTE b. NIBBLE c. WORD (16 bits) d. DOUBLEWORD (32 bits)
Last Answer : a. BYTE
Description : A name or number used to identify a storage location is called a. A byte b. A record c. An address d. All of above
Last Answer : c. An address
Description : The number of characters that can be stored in given physical space is a. Word length b. Byte c. Data density d. Field
Last Answer : c. Data density
Description : Which of the following magazines covers only the IBM PC and its compatibles? a. Byte b. PC Magazine c. Personal Computing d. Interface Age
Last Answer : b. PC Magazine
Description : A name or number used to identify a storage location devices? a. A byte b. A record c. An address d. All of above
Description : ____is used to control the cache with two new control bits not present in the 80386 microprocessor. What are the bits used to control the 8K byte cache? a) CR0, CD, NW b) CR0, NW, PWT c) Control Register Zero, PWT, PCD d) none
Last Answer : d) none
Description : The coprocessors operate in ______ with a processor on the same buses and with the same instruction _______. a) Parallel, byte stream. b) Series, byte stream. c) Series, bite stream d) Parallel, bite stream.
Last Answer : a) Parallel, byte stream.
Description : In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the ____. a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte d) LILO byte by byte.
Last Answer : a) FIFO byte by byte
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address register b. Memory data register c. Instruction registers d. Program counter
Last Answer : c. Instruction registers
Description : Which of the following registers is loaded with the contents of the memory location pointed by the PC? a. Memory address registers b. Memory data registers c. Instruction register d. Program counter
Last Answer : c. Instruction register
Description : In an 8085 microprocessor, the instruction CMP B has been executed while the contentsof accumulator is less than that of register B. As a result carry flag and zero flag will berespectively (A) set, reset (B) reset, set (C) reset, reset (D) set, set
Last Answer : (A) set, reset
Description : Which is not the control bus signal: a. READ b. WRITE c. RESET
Last Answer : c. RESET
Description : Serial port vector address is of _______. And causes an interrupt when ________. a) 0013H, either TI or RI flag is set b) 0023H, either TI or RI flag is reset c) 0013H, either TI or RI flag is reset d) 0023H, either TI or RI flag is set
Last Answer : a) 0013H, either TI or RI flag is set
Description : SP stand for: a. Stack pointer b. Stack pop c. Stack push d. None of these
Last Answer : a. Stack pointer
Description : SP stands for: a. Status pointer b. Stack pointer c. a and b d. None of these
Last Answer : b. Stack pointer
Description : Name of typical dedicated register is: a. PC b. IR c. SP d. All of these
Last Answer : d. All of these
Description : What is the output of the following code PUSH AL a) Decrement SP by 2 & push a word to stack b) Increment SP by 2 & push a word to stack c) Decrement SP by 2 & push a AL to stack d) Illegal
Last Answer : b) Increment SP by 2 & push a word to stack
Description : What is the size of SP register in 8085 microprocessor? A) 16 bits B) 8 bits C) 64 bits D) 48 bits
Last Answer : What is the size of SP register in 8085 microprocessor? A) 16 bits B) 8 bits C) 64 bits D) 48 bits
Description : ___ memory system which is discussed later can improve matters in this respect: a. Data memory b. Cache memory c. Memory d. None of these
Last Answer : b. Cache memory
Description : The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these
Last Answer : a. Read
Description : Which point to the ___ of the stack: a. TOP b. START c. MID
Last Answer : a. TOP
Description : 80386 support overall ___ addressing modes to facilitate efficient execution of higher level language programs. a) 9 b) 10 c) 11 d) 12
Last Answer : 11