Description : In 8279 Status Word, data is read when ________ pins are low, and write to the display RAM with ____________ are low. a) A0, CS, RD & A0, WR, CS. b) CS, WR, A0 & A0, CS, RD c) A0, RD & WR, CS d) CS, RD & A0, CS.
Last Answer : c) A0, RD & WR, CS
Description : In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the ____. a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte d) LILO byte by byte.
Last Answer : a) FIFO byte by byte
Description : The 8279 normally provides a maximum of _____ seven segment display interface with CPU. a) 8 b) 16 c) 32 d) 18
Last Answer : a) 8
Description : In 8279, the keyboard entries are debounced and stored in an _________, that is further accessed by the CPU to read the key codes. a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO
Last Answer : b) 8-byte FIFO
Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option ... b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : c) EA, high, external, internal
Description : In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller
Last Answer : a) 1, 8bit, single processor
Last Answer : c) 2, 9 bit, multiple processors
Description : In 8051 an external interrupt 1 vector address is of ________ and causes of interrupt if ____. a) 000BH, a high to low transition on pin INT1 b) 001BH, a low to high transition on pin INT1 c) 0013H, a high to low transition on pin INT1 d) 0023H, a low to high transition on pin INT1
Last Answer : a) 000BH, a high to low transition on pin INT1
Description : Serial port interrupt is generated, if ____ bits are seta) IE b) RI, IE c) IP, TI d) RI, TI
Last Answer : d) RI, TI
Description : Serial port interrupt is generated, if ____ bits are set a) IE b) RI, IE c) IP, TI d) RI, TI
Last Answer : a) IE
Description : The value memvar must be transferred to the ___: a. Computer b. CPU c. Both A and B d. None of these
Last Answer : b. CPU
Description : The CPU removes the ___ signal to complete the memory write operation: a. Read b. Write c. Both A and B d. None of these
Last Answer : a. Read
Description : If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM together with _____ memory and devices. a) EA, high, internal, external b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal
Last Answer : a) EA, high, internal, external
Description : When CS _____ the chip is not selected at all hence D7 to D0 are driven to high impedance state: a. High b. Low c. Medium d. Stand by
Last Answer : a. High
Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these
Last Answer : a. CPU
Description : The CPU sends out a ____ signal to indicate that valid data is available on the data bus: a. Read b. Write c. Both A and B
Last Answer : b. Write
Description : The information is transferred from the_____ and ____ specified register: a. MDR b. CPU c. Both A and B
Last Answer : c. Both A and B
Description : Virtual Mode Flag bit can be set using ____ instruction or any task switch operation only in the _____ mode a) IRET, Virtual b) POPF, Real c) IRET, protected d) POPF, protected
Last Answer : b) POPF, Real
Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode
Last Answer : c) bus width select
Last Answer : b) address valid strobe select
Description : CS stands for: a. Cable select b. Chip select c. Control select d. Cable system
Last Answer : b. Chip select
Description : A high quality CAD system uses the following for printing drawing and graphs a. Dot matrix printer b. Digital plotter c. Line printer d. All of the above
Last Answer : b. Digital plotter
Description : What is meant by interrupt?
Last Answer : Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine.
Description : List the four instructions which control the interrupt structure of the 8085 microprocessor.
Last Answer : • DI ( Disable Interrupts ) • EI ( Enable Interrupts ) • RIM ( Read Interrupt Masks ) • SIM ( Set Interrupt Masks )
Description : The external device is connected to a pin called the ______ pin on the processor chip. a. Interrupt b. Transfer c. Both d. None of these
Last Answer : a. Interrupt
Description : Which are the flags of status register: a. Over flow flag b. Carry flag c. Half carry flag d. Zero flag e. Interrupt flag f. Negative flag g. All of these
Last Answer : g. All of these
Description : The interrupt vector table of 80386 has been allocated ______ space starting from _______ to _______. a) 1Kbyte, 00000H, 003FFH b) 2Kbyte, 10000H, 004FFH c) 3Kbyte, 01000H, 007FFH d) 4Kbyte, 01000H, 009FFH
Last Answer : c) 3Kbyte, 01000H, 007FFH
Description : Serial port vector address is of _______. And causes an interrupt when ________. a) 0013H, either TI or RI flag is set b) 0023H, either TI or RI flag is reset c) 0013H, either TI or RI flag is reset d) 0023H, either TI or RI flag is set
Last Answer : a) 0013H, either TI or RI flag is set
Description : In 8096 we have _____interrupt sources and _______ interrupt vectors. a) 18, 8 b) 21, 6 c) 21, 8 d) 16, 8
Last Answer : c) 21, 8
Description : In 8051 which interrupt has highest priority? a)IE1 b)TF0 c)IE0 d)TF1
Last Answer : a)IE1
Description : If ______ and ________ connections are made so that an error condition in 8087 can interrupt to the processor. a) BHE, RQ/GT1 b) BUSY, TEST c) INT, NMI d) RQ/GT0, RQ/GT1
Last Answer : c) INT, NMI
Description : 8086 is interfaced to two 8259s (Programmable interrupt controllers). If 8259s are in master slave configuration the number of interrupts available to the 8086 microprocessor is a) 8 b) 16 c) 15 d) 64
Last Answer : c) 21,
Last Answer : c)IE0
Description : What is meant by Maskable interrupts? a) An interrupt which can never be turned off. b) An interrupt that can be turned off by the programmer. c) none
Last Answer : b) An interrupt that can be turned off by the programmer.
Description : RIM is used to check whether, ______ a) The write operation is done or not b) The interrupt is Masked or not c) a & b
Last Answer : b) The interrupt is Masked or not
Description : What is SIM? a) Select Interrupt Mask b) Sorting Interrupt Mask c) Set Interrupt Mask.
Last Answer : c) Set Interrupt Mask.
Description : Which interrupt is not level sensitive in 8085? a) RST6.5 is a raising edge-trigging interrupt. b) RST7.5 is a raising edge-trigging interrupt. c) a & b.
Last Answer : b) RST7.5 is a raising edge-trigging interrupt.
Description : Which interrupt has the highest priority? a) INTR b) TRAP c) RST6.5
Last Answer : c) RST6.5
Description : A hard copy would be prepared on a a. Line printer b. Dot matrix Printer c. Typewriter terminal d. All of the above
Last Answer : d. All of the above
Description : ___ memory system which is discussed later can improve matters in this respect: a. Data memory b. Cache memory c. Memory d. None of these
Last Answer : b. Cache memory
Description : Which point to the ___ of the stack: a. TOP b. START c. MID
Last Answer : a. TOP
Description : 80386 support overall ___ addressing modes to facilitate efficient execution of higher level language programs. a) 9 b) 10 c) 11 d) 12
Last Answer : 11
Description : The ___ bit decides whether it is a system descriptor or code/data segment descriptor a) P b) S c) D d) G
Last Answer : a) P
Description : SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset. a) 2 byte, 08H b) 8 bit, 07H c) 1 byte, 09H d) 8 bit, 06H
Last Answer : d) 8 bit, 06H
Description : 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv
Last Answer : c) 4, i,ii,iii
Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96
Last Answer : d) 16, MCS96
Description : The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,
Last Answer : a) 8 byte, on-chip 128 byte RAM.
Description : ___ Connection and the _______ instruction will solve the problem of synchronization between processor and coprocessor. a) INT & NMI, WAIT b) RQ/GT0 & RQ/GT1, FWAIT c) BUSY & TEST, FWAIT d) S0 & QS0, WAIT
Last Answer : b) RQ/GT0 & RQ/GT1, FWAIT