8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, register to register c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register

8096 has following features fill up the following,
i) ____ Register file,
ii) ____ I/O Ports
iii) ____ architecture.
a) 256 byte, five 8bit, register to register
b) 256 byte, four 8bit, register to register
c) 232 byte, five 8bit, register to register
d) 232 byte, six 8 bit, register to register
by

1 Answer

Answer :

c) 232 byte, five 8bit, register to register
by

Related questions

8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, register to register c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register

Description : 8096 has following features fill up the following, i) ____ Register file, ii) ____ I/O Ports iii) ____ architecture. a) 256 byte, five 8bit, register to register b) 256 byte, four 8bit, ... c) 232 byte, five 8bit, register to register d) 232 byte, six 8 bit, register to register

Last Answer : d) 232 byte, six 8 bit, register to register

In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller

Description : In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller

Last Answer : a) 1, 8bit, single processor

In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller

Description : In 8096, mode ____ of serial port are ___ modes commonly used for ____ communications. a) 1, 8bit, single processor b) 0, 7bit, multiple microcontroller c) 2, 9 bit, multiple processors d) 3, 8 bit, multiple microcontroller

Last Answer : c) 2, 9 bit, multiple processors

8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv

Description : 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv

Last Answer : c) 4, i,ii,iii

8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv

Description : 8096 has ___ general purpose I/O ports, Port 2 includes ______ of the following i) two quasi-bidirectional I/O lines ii) two output lines iii) four input lines iv) open drain outputs a) 4, i, iv b) 6, ii, iii c) 4, i,ii,iii d) 6, i, ii, iv

Last Answer : c) 4, i,ii,iii

The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,

Description : The SP is of ___ wide register. And this may be defined anywhere in the ______. a) 8 byte, on-chip 128 byte RAM. b) 8 bit, on chip 256 byte RAM. c) 16 bit,

Last Answer : a) 8 byte, on-chip 128 byte RAM.

In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode

Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode

Last Answer : c) bus width select

In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode

Description : In 8096, CCB bit 3 is ____. a) write strobe mode select b) address valid strobe select c) bus width select d) Internal read control mode

Last Answer : b) address valid strobe select

ROM d) 8 bit, on chip 128 byte RAM. 3. After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H

Description : ROM d) 8 bit, on chip 128 byte RAM. 3. After reset, SP register is initialized to address________. a) 8H b) 9H c) 7H d) 6H

Last Answer : c) 7H

How many synchronous and asynchronous modes are there in serial port of 8096? M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/1 Microprocessors and Microcontrollers/ Multiple Choice Questions Architecture of Micro controllers a) 2, 2 respectively b) 3,1 respectively c) 1, 3 respectively d) 1, 2 respectively

Description : How many synchronous and asynchronous modes are there in serial port of 8096? M. Krishna Kumar/IISc. Bangalore M5/V1/June 04/1 Microprocessors and Microcontrollers/ Multiple Choice Questions Architecture of Micro ... 2, 2 respectively b) 3,1 respectively c) 1, 3 respectively d) 1, 2 respectively

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Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Last Answer : d) 16, MCS96

Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Description : Intel 8096 is of ___ bit microcontroller family called as ______. a) 8, MCS51 b) 16, MCS51 c) 8, MCS96 d) 16, MCS96

Last Answer : d) 16, MCS96

8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option of using the ____ ROM or EPROM together with _____ memory and devices. a) EA, high, internal, external b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal

Description : 8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH 17. If the __ pin is ___ , then we have the option ... b) EA, low, internal, external c) EA, high, external, internal d) EA, low, external, internal

Last Answer : c) EA, high, external, internal

A byte consists of a. One bit b. Four bits c. Eight bits d. Sixteen bits

Description : A byte consists of a. One bit b. Four bits c. Eight bits d. Sixteen bits

Last Answer : c. Eight bits

In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C. a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2

Description : In 8255, under the I/O mode of operation we have __ modes. Under which mode will have the following features i) A 5 bit control port is available. ii) Three I/O lines are available at Port C. a) 3, Mode2 b) 2, Mode 2 c) 4, Mode 3 d) 3, Mode 2

Last Answer : a) 3, Mode2

The original ASCII code used…bits of each byte, reserving that last bit for error checking a. 5 b. 6 c. 7 d. 8

Description : The original ASCII code used…bits of each byte, reserving that last bit for error checking a. 5 b. 6 c. 7 d. 8

Last Answer : c. 7

A 32 bit microprocessor has the word length equal to a. 2 byte b. 32 byte c. 4 byte d. 8 byte

Description : A 32 bit microprocessor has the word length equal to a. 2 byte b. 32 byte c. 4 byte d. 8 byte

Last Answer : c. 4 byte

SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset. a) 2 byte, 08H b) 8 bit, 07H c) 1 byte, 09H d) 8 bit, 06H

Description : SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset. a) 2 byte, 08H b) 8 bit, 07H c) 1 byte, 09H d) 8 bit, 06H

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The 8051 microcontroller is of ___pin package as a ______ processor. a) 30, 1byte b) 20, 1 byte c) 40, 8 bit

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In 8279, the keyboard entries are debounced and stored in an _________, that is further accessed by the CPU to read the key codes. a) 8-bit FIFO b) 8-byte FIFO c) 16 byte FIFO d) 16 bit FIFO

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Last Answer : c) 40, 8 bit

The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register

Description : The microprocessor can read/write 16 bit data from or to ________ A. memory B. I /O device C. processor D. register

Last Answer : The microprocessor can read/write 16 bit data from or to memory 

____is used to control the cache with two new control bits not present in the 80386 microprocessor. What are the bits used to control the 8K byte cache? a) CR0, CD, NW b) CR0, NW, PWT c) Control Register Zero, PWT, PCD d) none

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Last Answer : d) none

In 8096 we have _____interrupt sources and _______ interrupt vectors. a) 18, 8 b) 21, 6 c) 21, 8 d) 16, 8

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In 8096 we have _____interrupt sources and _______ interrupt vectors. a) 18, 8 b) 21, 6 c) 21, 8 d) 16, 8

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In 8279 Strobed input mode, the control line goes low. The data on return lines is strobed in the ____. a) FIFO byte by byte b) FILO byte by byte c) LIFO byte by byte d) LILO byte by byte.

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Last Answer : a) FIFO byte by byte

A stack is a. an 8-bit register in the microprocessor b. a 16-bit register in the microprocessor c. a set of memory locations in R/WM reserved for storing information temporarily during the execution of computer

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How many bit of MAR register: a. 8-bit b. 16-bit c. 32-bit d. 64-bit

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How many bit stored by status register: a. 1 bit b. 4 bit c. 6 bit d. 8 bit

Description : How many bit stored by status register: a. 1 bit b. 4 bit c. 6 bit d. 8 bit

Last Answer : a. 1 bit

In 8087, _______ many register stack are there? And of _____ registers. These registers are used as _________ stack. a) 7, 40 bit, FIFO. b) 8, 60 bit, LILO. c) 8, 80 bit, LIFO d) 7, 80 bit, FILO.

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.In an 8085 based system, the maximum number of input output devices can be connectedusing I/0 mapped I/O method isa) 64 b) 512 c) 256 d) 65536

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Last Answer : b) 512

Which is not the main architectural feature of Power PC: a. It is not based on RISC b. Superscalar implementation c. Both 32 & 64 Bit d. Paged Memory management architecture

Description : Which is not the main architectural feature of Power PC: a. It is not based on RISC b. Superscalar implementation c. Both 32 & 64 Bit d. Paged Memory management architecture

Last Answer : a. It is not based on RISC

8096 write-protected mode, no code can write to memory address between __. a) 2020 to 3FFFH b) 8000 to FFFFH c) 2000 to 3FFFH d) 2020 to 202FH

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Last Answer : c) 2000 to 3FFFH

How many generation of microprocessor: a. Four b. Five c. Six d. Three

Description : How many generation of microprocessor: a. Four b. Five c. Six d. Three

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A stack pointer is a. a 16-bit register in the microprocessor that indicate the beginning of the stack memory. b. a register that decodes and executes 16-bit arithmetic expression. c. The first memory location where a subroutine address is stored. d. a register in which flag bits are stored

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Which bit of TMOD will exactly configure timer / counter as a timer or counter. i) TMOD.6 of C/T for timer 1 ii) TMOD.6 of C/T for timer 0 iii) TMOD.2 of C/T for timer 0 iv) TMOD.2 of C/T for timer 1 a) i, ii b) ii, iv c) i, iii d) iii, iv

Description : Which bit of TMOD will exactly configure timer / counter as a timer or counter. i) TMOD.6 of C/T for timer 1 ii) TMOD.6 of C/T for timer 0 iii) TMOD.2 of C/T for timer 0 iv) TMOD.2 of C/T for timer 1 a) i, ii b) ii, iv c) i, iii d) iii, iv

Last Answer : a) i, ii

Which of the following instruction is of logical instructions? i) CPL A ii) JC rel iii) DA A iv) ANL A, Rn v) RR A vi) CPL bit a) i, v b) v, iii, I c) iv, ii d) v, iii, ii

Description : Which of the following instruction is of logical instructions? i) CPL A ii) JC rel iii) DA A iv) ANL A, Rn v) RR A vi) CPL bit a) i, v b) v, iii, I c) iv, ii d) v, iii, ii

Last Answer : c) iv, i

Which of the following is of bit operations? i) SP ii) P2 iii) TMOD iv) SBUF v) IP a) ii, v only b) ii, iv, v only c) i, v only d) iii, ii only

Description : Which of the following is of bit operations? i) SP ii) P2 iii) TMOD iv) SBUF v) IP a) ii, v only b) ii, iv, v only c) i, v only d) iii, ii only

Last Answer : c) i, v only

Which of the following is of bit operations? i) SP ii) P2 iii) TMOD iv) SBUF v) IP a) ii, v only b) ii, iv, v only c) i, v only d) iii, ii only

Description : Which of the following is of bit operations? i) SP ii) P2 iii) TMOD iv) SBUF v) IP a) ii, v only b) ii, iv, v only c) i, v only d) iii, ii only

Last Answer : a) ii, v only

The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these

Description : The ____ place the data from a register onto the data bus: a. CPU b. ALU c. Both A and B d. None of these

Last Answer : a. CPU

The information is transferred from the_____ and ____ specified register: a. MDR b. CPU c. Both A and B

Description : The information is transferred from the_____ and ____ specified register: a. MDR b. CPU c. Both A and B

Last Answer : c. Both A and B

How bit microprocessor inexpensive a separate interface is provided with I/O device: a. 2 bit b. 4 bit c. 8 bit d. 32 bit

Description : How bit microprocessor inexpensive a separate interface is provided with I/O device: a. 2 bit b. 4 bit c. 8 bit d. 32 bit

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What is the difference between. (i) BIT and BYTE (ii) RAM and ROM (iii) C.U. and A.L.U (iv) Hardware and Software (v) Personal computer and mainframe

Description : What is the difference between. (i) BIT and BYTE (ii) RAM and ROM (iii) C.U. and A.L.U (iv) Hardware and Software (v) Personal computer and mainframe

Last Answer : Personal computer and mainframe: Personal Computer (PC): Short for personal computer or IBM PC. The first personal computer produced by IBM was called the PC, and increasingly the term ... mainframes and minicomputers is vague, depending really on how the manufacturer wants to market its machines.

Define following : i. Radix ii. Bit iii. Nibble iv. Byte

Description : Define following : i. Radix ii. Bit iii. Nibble iv. Byte

Last Answer : i. Radix- the base to a given number system is called as radix.  ii. Bit- Single ‗1‘ or ‗0‘ is called as a bit.  iii. Nibble- a group of 4 bits is called as nibble  iv. Byte- a group of 8 bits is called as a byte.

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Last Answer : a. byte

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Description : In linear decoding address bus of 16-bit wide can connect only ____ of RAM. a. 16 KB b. 6KB c. 12KB d. 64KB

Last Answer : b. 6KB

Virtual Mode Flag bit can be set using ____ instruction or any task switch operation only in the _____ mode a) IRET, Virtual b) POPF, Real c) IRET, protected d) POPF, protected

Description : Virtual Mode Flag bit can be set using ____ instruction or any task switch operation only in the _____ mode a) IRET, Virtual b) POPF, Real c) IRET, protected d) POPF, protected

Last Answer : b) POPF, Real

In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor communication and is of ____ bit address. a) SM1, 9EH b) TB8 , 9CH c) SM2 , 9DH d) SM0, 9FH

Description : In modes 2 and 3, if _____ bit of SCON bit is set will causes enable multiprocessor communication and is of ____ bit address. a) SM1, 9EH b) TB8 , 9CH c) SM2 , 9DH d) SM0, 9FH

Last Answer : c) SM2 , 9DH

Interface electronic circuit is used to interconnect I/O devices to a computer’s CPU or a. ALU b. Memory c. Buffer d. Register

Description : Interface electronic circuit is used to interconnect I/O devices to a computer’s CPU or a. ALU b. Memory c. Buffer d. Register

Last Answer : b. Memory